cc2500驱动程序(Atmega16)

1、cc2500 驱动程序(Atmega16)头文件：cc2500.h#ifndef _CC2500_H#define _CC2500_H/ CC2500 管脚RFO0 / PB4RF_IO1 / PD2RF_IO2 / PD3#define CC2500_CSn#define CC2500_GD00#define CC2500_GDO2/定义数据包 #define CC2500_PKT_LEN 80 typedef struct u8_t bufCC2500_PKT_LEN; u8_t len; packet_2500_t;extern packet_2500_t tx_pkt_2500;ext

2、ern packet_2500_t rx_pkt_2500;extern u8 textern u8_t/ PATABLEextern u8 textern u8_trx_state_2500; rx_flag_2500;(1 dBm output power) paTable;paTableLe n;void cc_wait(u16_t cycles);void cc_spi_setup(void);u8_t count);u8_t count);void cc_spi_write_reg(u8_t addr, u8_t value); void cc_spi_write_burst_reg

3、(u8_t addr, u8_t *buffer, u8_t cc_spi_read_reg(u8_t addr);void cc_spi_read_burst_reg(u8_t addr, u8_t *buffer, u8_t cc_spi_read_status(u8_t addr);void cc_spi_strobe(u8_t strobe);void cc_powerup_reset(void);void cc_write_settings(void);void cc_send_packet(u8_t *tx_buf, u8_t size); u8_t cc_receive_pack

4、et(u8_t *rx_buf, u8_t *length); / test function void cc_test(void); #en dif实现代码：cc2500.c#include <avr/io.h>#include <avr/interrupt.h>#include <stdlib.h>#include "common.h"#include "ccxxxO_reg.h"#include "cc2500.h"#include "key.h"/数据包packet_25

5、00_t tx_pkt_2500;packet_2500_t rx_pkt_2500;u8_t rx_state_2500;u8_t rx_flag_2500;void cc_wait(u16_t cycles)while (cycles > 6) cycles -= 6;/ cc2500外部管脚配置void cc_spi_setup(void)DDRB |= CC2500_CSn;PORTB |= CC2500_CSn;PORTD |= CC2500_GDO0; / 使能上拉/配置SPI总线/SPSR |= (1<vSPI2X); / 设置 SPI 时钟倍速SPCR |= (1&

6、lt;<SPE)|(1vvMSTR);/ 使能 SPI 接口，主机模式cli(); /清所有中断MCUCR |= 0x02; / INT0 下降沿触发GICR |= 0x40; / 使能 INT0void cc_spi_write_reg(u8_t addr, u8_t value)/ CS enablePORTB &= CC2500_CSn;/ wait for CCxxxx readywhile (PINB&SPI_MISO);/ Clear flagSPSR = 0x00;/ Send addressSPDR = addr;/ Wait for TX to fini

7、shwhile (!(SPSR & (1<<SPIF);cc_wait(75);/ Clear flagSPSR = 0x00;/ Load data for TX after addrSPDR = value;/ Wait for end of addr TXwhile (!(SPSR & (1<<SPIF);cc_wait(75);/ CS disablePORTB |= CC2500_CSn;void cc_spi_write_burst_reg(u8_t addr, u8_t *buffer, u8_t count)u8_t i;/ CS ena

8、blePORTB &= CC2500_CSn;/ Wait for CCxxxx readywhile (PINB&SPI_MISO);/ Clear flagSPSR = 0x00;/ Send addressSPDR = addr|TI_CCxxx0_WRITE_BURST;/ Wait for TX to finishwhile (!(SPSR & (1<<SPIF);for (i=0; i<count; i+) / Clear flagSPSR = 0x00;SPDR = bufferi;while (!(SPSR & (1<&l

9、t;SPIF);cc_wait(30);cc_wait(30);/ Clear flagSPSR = 0x00;/ CS disablePORTB |= CC2500_CSn;u8_t cc_spi_read_reg(u8_t addr)u8_t x;/ CS enablePORTB &= CC2500_CSn;/ Wait for CCxxxx ready,while (PINB&SPI_MISO);/ Clear flag set during addr TXSPSR = 0x00;/ Send AddressSPDR = addr|TI_CCxxx0_READ_SINGL

10、E;/ Wait for TXBUF readywhile (!(SPSR & (1<<SPIF);cc_wait(75);/ Clear flag set during addr TXSPSR = 0x00;/ Load dummy byte for TX after addrSPDR = 0;/ Wait for end of dymmy byte TXwhile (!(SPSR & (1<<SPIF);cc_wait(75);/ Read datax = SPDR;cc_wait(45);cc_wait(45);/ CS disablePORTB

11、|= CC2500_CSn;return x;void cc_spi_read_burst_reg(u8_t addr, u8_t *buffer, u8_t count)u8_t i;/ CS enablePORTB &= CC2500_CSn;/ Wait for CCxxxx readywhile (PINB&SPI_MISO);/ clear flagSPSR = 0x00;/ Send addressSPDR = addr|TI_CCxxx0_READ_BURST;/ Wait for txbuf readywhile (!(SPSR & (1<<

12、SPIF); cc_wait(60);for (i=0; i<count; i+) SPSR = 0x00; / Clear flag/ Initiate next data RX, meanwhile SPDR = 0;/ wair for end of 1st data byte TX while (!(SPSR & (1<<SPIF); cc_wait(30);bufferi = SPDR;/ Clear flagSPSR = 0x00;/ CS diablePORTB |= CC2500_CSn;u8_t cc_spi_read_status(u8_t add

13、r)u8_t x;/ CS enablePORTB &= CC2500_CSn;/ Wait for CCxxxx readywhile (PINB&SPI_MISO);/ Clear flag set during last writeSPSR = 0x00;/ Send addressSPDR = addr|TI_CCxxx0_READ_BURST;/ Wait for TX to finishwhile (!(SPSR & (1<<SPIF);/ Clear flag set during last writeSPSR = 0x00;/ Dummy w

14、rite so we can read dataSPDR = 0;/ Wait for RX to finishwhile (!(SPSR & (1<<SPIF); cc_wait(45);cc_wait(45);/ Read datax = SPDR;/ CS disablePORTB |= CC2500_CSn; return x;void cc_spi_strobe(u8_t strobe)/ CS enablePORTB &= CC2500_CSn;/ Wait for CCxxxx ready while (PINB&SPI_MISO);/ Cle

15、ar flag set during last write SPSR = 0x00;/ Send strobeSPDR = strobe;/ Wait for TX to finishwhile (!(SPSR & (1<<SPIF);/ CS disablePORTB |= CC2500_CSn;void cc_powerup_reset(void)/ CS disablePORTB |= CC2500_CSn;cc_wait(30);/ CS enablePORTB &= CC2500_CSn; cc_wait(30);/ CS disablePORTB |=

16、CC2500_CSn; cc_wait(45);/ CS enablePORTB &= CC2500_CSn;/ Wait for CCxxxx readywhile (PINB&SPI_MISO);/ clear flagSPSR = 0x00;/ reset CCxxxx chipSPDR = TI_CCxxx0_SRES;/ Wait for end of addr TXwhile (!(SPSR & (1<<SPIF);cc_wait(45);cc_wait(45);cc_wait(45);/ CS disablePORTB |= CC2500_CS

17、n;/ CC2500/ Product = CC2500/ Crystal accuracy = 40 ppm/ X-tal frequency = 26 MHz/ RF output power = 0 dBm/ RX filterbandwidth = 540.000000 kHz/ Deviation = 0.000000/ Return state: Return to RX state upon leaving either TX or RX/ Datarate = 250.000000 kbps/ Modulation = (7) MSK/ Manchester enable =

18、(0) Manchester disabled/ RF Frequency = 2433.000000 MHz/ Cha nnel spaci ng = 199.950000 kHz/ Channel number = 0/ Optimization = Sensitivity/ Sync mode = (3) 30/32 sync word bits detected/ Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX/ CRC operation = (1) CRC calculation in TX and C

19、RC check in RX en abled/ Forward Error Correction = (0) FEC disabled/ Length configuration = (1) Variable length packets, packet length config ured by the first received byte after sync word./ Packetlength = 255/ Preamble count = (2) 4 bytes/ Append status = 1/ Address check = (0) No address check/

20、FIFO autoflush = 0/ Device address = 0Clock/ GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet/ GDO2 signal selection = (11) Serialvoid cc_write_settings(void)#if 0OxOB); / GDO2 output pin con/ Write register settings cc_spi_write_r

21、eg(TI_CCxxx0_IOCFG2, fig.0x3A); / GDO2 output pin conficc_spi_write_reg(TI_CCxxx0_IOCFG2,g.0x06); / GDO0 output pin concc_spi_write_reg(TI_CCxxx0_IOCFG0,0xFF); / Packet length.0x05);fig./ Packet automation/ Packet automation0x05);cc_spi_write_reg(TI_CCxxx0_PKTLEN, cc_spi_write_reg(TI_CCxxx0_PKTCTRL1

22、, con trol.cc_spi_write_reg(TI_CCxxx0_PKTCTRL0,0x01); /0x00); / Channel number.0x07); / Freq synthesizer contDevice address.con trol.0x00); / Freq synthesizer contcc_spi_write_reg(TI_CCxxx0_ADDR, cc_spi_write_reg(TI_CCxxx0_CHANNR, cc_spi_write_reg(TI_CCxxx0_FSCTRL1, rol.cc_spi_write_reg(TI_CCxxx0_FS

23、CTRL0, rol.0x5D); / Freq controlword, hig#if 0cc_spi_write_reg(TI_CCxxx0_FREQ2,0x93); / Freq controlword, midh bytecc_spi_write_reg(TI_CCxxx0_FREQ1,0xB1); / Freq controlword, lowbyte.cc_spi_write_reg(TI_CCxxx0_FREQ0,byte.#en dif0x5c);/ Freqcon trolword,higcc_spi_write_reg(TI_CCxxx0_FREQ2,h bytecc_sp

24、i_write_reg(TI_CCxxx0_FREQ1, byte.cc_spi_write_reg(TI_CCxxx0_FREQ0, byte.cc_spi_write_reg(TI_CCxxx0_MDMCFG4,0x80);0x00);n.cc_spi_write_reg(TI_CCxxx0_MDMCFG3,n.cc_spi_write_reg(TI_CCxxx0_MDMCFG2,n.cc_spi_write_reg(TI_CCxxx0_MDMCFG1,n.cc_spi_write_reg(TI_CCxxx0_MDMCFG0,n.cc_spi_write_reg(TI_CCxxx0_DEV

25、IATN, SK mod en)cc_spi_write_reg(TI_CCxxx0_MCSM1 Mach inecc_spi_write_reg(TI_CCxxx0_MCSM0 Mach inecc_spi_write_reg(TI_CCxxx0_FOCCFG, s. Configcc_spi_write_reg(TI_CCxxx0_BSCFG, on fig.cc_spi_write_reg(TI_CCxxx0_AGCCTRL2, cc_spi_write_reg(TI_CCxxx0_AGCCTRL1, cc_spi_write_reg(TI_CCxxx0_AGCCTRL0, cc_spi

26、_write_reg(TI_CCxxx0_FREND1, rati on.cc_spi_write_reg(TI_CCxxx0_FREND0, rati on.cc_spi_write_reg(TI_CCxxx0_FSCAL3, r cal.cc_spi_write_reg(TI_CCxxx0_FSCAL2, cal./ Freq/ Freqcon trolcon trol0x2D); / Modem0x3B); / Modem0x73); / Modem0x22); / Modem0xF8); / Modemword,word,midlowcon figuratiocon figuratio

27、con figuratiocon figuratiocon figuratio0x00); / Modem dev (when F0x3F); /MainRadio Cntrl State,0x18); /MainRadio Cntrl State0x1D); / Freq Offset Compen0x1C); / Bit synchronization c0xC7); / AGC control.0x00); / AGC control.0xB2); / AGC control.0xB6); / Front end RX configu0x10); / Front end0xEA); /

28、Frequency0x0A); / FrequencyRX configusyn thesizesyn thesizercc_spi_write_reg(TI_CCxxx0_FSCAL1,0x00); / Frequencysyn thesizer0x11); / Frequency synthesizer0x59); / Frequency synthesizer0x88); / Various test settings.0x31); / Various test settings. OxOB); / Various test sett in gs.cal.cc_spi_write_reg

29、(TI_CCxxxO_FSCALO, cal.cc_spi_write_reg(TI_CCxxxO_FSTEST, cal.cc_spi_write_reg(TI_CCxxxO_TEST2,cc_spi_write_reg(TI_CCxxxO_TEST1,cc_spi_write_reg(TI_CCxxxO_TESTO, #en dif#if 0cc_spi_write_reg(TI_CCxxx0_MCSM00x18); / MainRadio Cntrl State/ Write register settings cc_spi_write_reg(TI_CCxxx0_IOCFG2, cc_

30、spi_write_reg(TI_CCxxx0_IOCFG0, cc_spi_write_reg(TI_CCxxxO_PKTLEN, cc_spi_write_reg(TI_CCxxxO_PKTCTRL1, OxOB); / GDO2 output pin con fig. 0x06); / GDOO output pin con fig. OxFF); / Packet length.0x05); / Packet automation concc_spi_write_reg(TI_CCxxx0_MCSM00x18); / MainRadio Cntrl State0x22); / Pack

31、et automation control.cc_spi_write_reg(TI_CCxxxO_PKTCTRLO, trol.cc_spi_write_reg(TI_CCxxx0_MCSM00x18); / MainRadio Cntrl Statecc_spi_write_reg(TI_CCxxxO_ADDR, cc_spi_write_reg(TI_CCxxxO_CHANNR, cc_spi_write_reg(TI_CCxxx0_FSCTRL1, cc_spi_write_reg(TI_CCxxx0_FSCTRL0, cc_spi_write_reg(TI_CCxxxO_FREQ2,

32、byte cc_spi_write_reg(TI_CCxxx0_FREQ1, yte.cc_spi_write_reg(TI_CCxxx0_FREQ0, yte.cc_spi_write_reg(TI_CCxxxO_MDMCFG4, cc_spi_write_reg(TI_CCxxxO_MDMCFG3, cc_spi_write_reg(TI_CCxxxO_MDMCFG2, cc_spi_write_reg(TI_CCxxx0_MDMCFG1, cc_spi_write_reg(TI_CCxxx0_MDMCFG0, cc_spi_write_reg(TI_CCxxxO_DEVIATN, mod

33、 en) cc_spi_write_reg(TI_CCxxx0_MCSM1 Mach ine0x01); / Device address.0x00); / Channel number.0x12); / Freq synthesizer control.0x00); / Freq synthesizer control.0x5c);/Freqcontrolword,high0x80);/Freqcontrolword,midb0x00);/Freqcontrolword,lowb0x2D); / Modem configuration. 0x3B); / Modem configuratio

34、n. 0xF3); / Modem configuration.0x22); / Modem configuration.0xF8); / Modem configuration.0x00); / Modem dev (when FSK0x3F); / MainRadio Cntrl Statecc_spi_write_reg(TI_CCxxx0_MCSM00x18); / MainRadio Cntrl StateOx1D); / Freq Offset Compens.Mach ine cc_spi_write_reg(TI_CCxxx0_FOCCFG, Config cc_spi_wri

35、te_reg(TI_CCxxx0_BSCFG, g. cc_spi_write_reg(TI_CCxxx0_AGCCTRL2, cc_spi_write_reg(TI_CCxxx0_AGCCTRL1, cc_spi_write_reg(TI_CCxxx0_AGCCTRL0, cc_spi_write_reg(TI_CCxxx0_FREND1, tio n. cc_spi_write_reg(TI_CCxxx0_FREND0, ion. cc_spi_write_reg(TI_CCxxx0_FSCAL3, al. cc_spi_write_reg(TI_CCxxx0_FSCAL2, al. cc

36、_spi_write_reg(TI_CCxxx0_FSCAL1, al. cc_spi_write_reg(TI_CCxxx0_FSCAL0, al. cc_spi_write_reg(TI_CCxxx0_FSTEST, al. cc_spi_write_reg(TI_CCxxx0_TEST2, cc_spi_write_reg(TI_CCxxx0_TEST1, cc_spi_write_reg(TI_CCxxx0_TEST0, #en dif #if 1/ Write register settings cc_spi_write_reg(TI_CCxxx0_IOCFG2, fig.cc_sp

37、i_write_reg(TI_CCxxx0_IOCFG2, g.cc_spi_write_reg(TI_CCxxx0_IOCFG0, fig.cc_spi_write_reg(TI_CCxxx0_PKTLEN, cc_spi_write_reg(TI_CCxxx0_PKTCTRL1, con trol.cc_spi_write_reg(TI_CCxxx0_PKTCTRL0,0x1C); / Bit synchronization confi0xC7); / AGC0x00); / AGC0xB0); / AGC0xB6); /0x10); /0xEA); /0x0A); /0x00);0x11

38、);0x59);0x88);0x31);0x0B);/con trol. con trol. con trol.Front endFront endFreque ncyFreque ncyFreque ncyFreque ncyFreque ncy/ Various/ VariousVarious/0x0B);0x3A);RX configuraRX configuratsyn thesizersyn thesizersyn thesizersyn thesizersyn thesizertesttesttestsett ings.sett ings.setti ngs./ GDO2 outp

39、ut pin con/ GDO2 output pin confi0x06); / GDO0 output pin con0xFF);0x05);0x05);/ Packet length./ Packet automation/ Packet automation0x01); / Device address.0x00); / Channel number.0x06); / Freq synthesizer cont0x00); / Freq synthesizer cont0x5c);/Freqcontrolword,hig0x80);/Freqcontrolword,mid0x00);/

40、Freqcontrolword,low0x78); / Modem configuratio0x93); / Modem configuratio0x03); / Modem configuratio0x22); / Modem configuratio0xF8); / Modem configuratio0x44); / Modem dev (when F0x3F); /MainRadio Cntrl State0x18); /MainRadio Cntrl State0x16); / Freq Offset Compens.0x6C); / Bit synchronization c0x4

41、3); / AGC control.0x40); / AGC control.0x91); / AGC control.con trol.cc_spi_write_reg(TI_CCxxxO_ADDR, cc_spi_write_reg(TI_CCxxxO_CHANNR, cc_spi_write_reg(TI_CCxxxO_FSCTRL1, rol.cc_spi_write_reg(TI_CCxxxO_FSCTRLO, rol.cc_spi_write_reg(TI_CCxxxO_FREQ2,h bytecc_spi_write_reg(TI_CCxxxO_FREQ1, byte.cc_sp

42、i_write_reg(TI_CCxxxO_FREQO, byte.cc_spi_write_reg(TI_CCxxxO_MDMCFG4, n.cc_spi_write_reg(TI_CCxxxO_MDMCFG3, n.cc_spi_write_reg(TI_CCxxxO_MDMCFG2, n.cc_spi_write_reg(TI_CCxxxO_MDMCFG1, n.cc_spi_write_reg(TI_CCxxxO_MDMCFGO, n.cc_spi_write_reg(TI_CCxxxO_DEVIATN, SK mod en)cc_spi_write_reg(TI_CCxxx0_MCS

43、M1Mach inecc_spi_write_reg(TI_CCxxx0_MCSM0Mach inecc_spi_write_reg(TI_CCxxx0_FOCCFG,Configcc_spi_write_reg(TI_CCxxxO_BSCFG, on fig.cc_spi_write_reg(TI_CCxxxO_AGCCTRL2,cc_spi_write_reg(TI_CCxxx0_AGCCTRL1,cc_spi_write_reg(TI_CCxxx0_AGCCTRL0, rati on.cc_spi_write_reg(TI_CCxxx0_FREND1,0x56); / Front end

44、 RX configu0x10); / Front end RX configu0xA9); / Frequency synthesizer OxOA); / Frequency synthesizer 0x00); / Frequency synthesizer 0x11); / Frequency synthesizer 0x59); / Frequency synthesizer0x88); / Various test settings.0x31); / Various test settings. OxOB); / Various test settings.tx_buf, size); / Write TX dcli(); cc_spi_strobe(TI_CCxxx0_STX); while (PIND&CC25OO_GDOO) while (PIND&CC25OO_GDOO)cc_spi_write_reg(TI_CCxxxO_FRENDO, rati on.cc_spi_write_reg(TI_CCxxxO_FSCAL3, cal.cc_spi_write_reg(TI_CCxxxO_FSCAL2, cal