EDA技术实用教程

1、EDA技术实用教程Quartusl 3?用向导5.1?设计流程 ?1 ?建立工作库文件夹和编辑设？文件IT殛 Vlhrllll mW1-LIigjiARY IEEE?呻I: 1KIXK.STI3_|.i0aALI-.?LISE IEEEWTD_Li(KI(uKIEIGfl!；DALLi：lENTITY CNT10_r3I nCOUT s OUT SPND CWTIQ； 上胆HHTI忙于口仇1PORT (CLK, RSTUT i IN STI' LOGIC；Wl'fSd)BiaiNPROCESS 口 VJLRI2EIIEGIN IF ESI ELS 11 IT tUJltfriQ

2、B2图5?选择编辑文件的语言类型，键入源程序并存盘5?创建工程V/hat is he name of this project? |CNT1OV/ht i$ theof the jop-level design entilv fm thi$ proict? Thi$ name case sensitive and Eu*tewactly match the entity name in the design Hie.ICNTIOUse Existing Projecl Settings .图5-2 利用 “NW PrejecGWizard” 创建工程cnt10?pageSelect the d

3、esign files you want to include in the project Click Add All to add all design files in the project directory to the project Note: you can always add design files lo lhe project later.File nameTypeCNTIOvhdVHDL FileFile name:35pREO 3 orf图5-3将所有相关的文件都加入进此工程j Wnw Projoct WiiirdE Family 1 Device Sotting

4、sjcIclI fsillily arid Jcvii-eyuu vanl iotdiyet fur cumpild.iLriFamily： CpclonellT arget deviceAuiu devius >bIecIsiJ Ue Fitter Specific device :ebecied in Xvaible devices' istShow ri Adlatie device' list PckcigePin £nunlTUFF而1.2VSpeed ladc匚cub v jlioye* Show Advanced DevicesNameLEsMem

5、-or.Embed.PLLhP2LSH44LH4HUH119806261EP2C&T144IS119S0S2S2EP2CBT144CS825&1658 匪站2EPXfiTUdie£2確12图?4选择目标器件EP2C5T14牝8Convert MAX+PLUS II ProjectXlAllows you to convert existing MAX+PLUS II projects and assignments into a new Qurtus II project.图5-?将Max+plUSlI工程转换为Q?irtusll工程?5.1.3编译前设置Cit&am

6、p;gorp：GenefdHiesUser Libraries Current ProjectDevice+ Timing Anaisis Settings* EDA Tool Settings+ CcrnpiaHon Piocejs Settings-Analysis L Sjnthesis SettingsVHDLIputVerilog HDL IripUtDefaut PaametefsSvnthe5tfNetlist Optimeahons-Fitter Set&igsPhjjsicd Syndissis OpivnizionsA$semtilefDesign Asstsirt

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8、on26TT82Available devices:Setectthe 佃斶 and device you 丹"to target for conpjbon.图5?选择目标器件？P2C?T144?8Device ft Pin Opt innsXDual-Purpose FinsVoltagePin PlacementError Detection CRCGetter alC onf i gurat i onPrcgr wnh n£ Fli tsUnus«d PinsSpecify general device oprons, These options are n

9、ot dependent on the coiVigiMation scheme.Options:Auto barcodeJ TAG user code 132-bit heKadecimafJ. ED325G7图5-7选择配置器件的工作方式图5?选择配置器件和编程方式514全程编译Firm- S1W 5 K 12-20:23 2D05弓Build IBS 06/22/2flK S? 1 器 hill皿nrreCMT10CydarutEiriC3TJ44：0Fl-inir Si A-Liift iQumr Iue £1 *dr= s :-XL 陥vision S*JTitTu|i l

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13、ncludiTi 0 ti ax., in s.om：-c* fil« CBTTLO. vhdErrr； 9*aatw II 血心昨l$ 电 Svxhcsi； wm3 cr-rsrs. 0 mitalics图5?全程编译后出现报错信息51?时序仿真Device Design Files Other FilesAHDL Include FileBlock Symbol FileChain Description FileHexadecimal (Iritel'ForrriaQ File Logic Analyzer Interface FileM ernoiy Initiali

14、zation File SignalTap II FileTel Scripl FileText FileVector Waveform File图5?0选择编辑矢量波形文件毯 CNTIQYhd色 CompilaiionReport-FlowSummay 词 Wavefanul.vwfHI hit *r Tirnt Bur. ID. 55 ni< * Poi.itt*r: T= 75 ns lAturv*!:-2. B ni Sturt：End：IT weVtlnt at10 55 ns)ps10.0 ns20.?10 5!5 nsJ图5-?1波形编辑器图5?2设置仿真时间长度图5?3

15、vW激励波形文件存盘V*1tl .I D. 5.CU£A 0ESTB 010.241 us10. 55 mCOIRBIrzix> > -图5?4向波形编辑器拖入信号节点ClodBase waveform onC Clack settings:I3W Time period;Peiiod:12.0Phase：|CIOB9 TLU? cpcle XJ: S jJD 礼 | Cancel图5-15设置时钟C?K的周期Name:Ivpe：Value type:Radix:Bus width:Unsigned Decimal3D isplay gray code count as

16、binary count图5?6选择总线数据格式CLXEXCOVT10.24 a15.肉如 20 48 hi工manLnirwrLTLnLJErLrLTL图5-17设置好的激励波形图: Trnitig Setlirgs* EDA Tool S*： CWbiicri Frocks Setthgj F Analysis le $ynlh$i$ 5武ting字 VHDLIrtput VdilogHlDLInpy Defadl Parameleis SynUiesis OptimGal-icnsH FMefSetlingsPascal Sjpn thesis Optnnzations Assemble

17、rDesign AtshlarlSignalTafj II Logic AnaijeiLogic Anazei InteifaceProbe Settings|irnulon mode jiwig S rnulion npiJ: |CNTlO,v*4Siirnulalnri pefiqd俗 Run Emulation uhbl 对I veda £bMuli an# used£nd simulation at:.Smuhla 5呂加护SimdMion Power丽 Automaitically add pins to simJaKon 唧Iput waveforms 厂 Ch

18、eck out pusI- Setup and Ijold time Yiofation detection旺 £kchctaeclm |1|rw 二丽 S inulalion overageeportingBepocl Seltings.图5-18选择仿真控制畑mt ft51015.36 is'20. Z2S.6 輕30.72 址Kntess理30.55 nsJCLKB 0jirLrLnrLrLrLrLrLrmrLrLrLrLrLjElfB 0KTB 竺OUTB 0LLLLLU14LLLLU-L2X a GlU 0 ;fome2 Y 3 1OS 3b arL甘-M(2B 0

19、J-CO(LB 01J"Lcq(oB 0rn1|一_r-LJLULJL图5-19仿真波形输出Fit in Window Ctrl+WZoom InCtrl+SpaceZoom gutCtrl+Shift+SpaceZoom.,图5-20选择全时域显示5？应用RTL ?路图观察器图5-2?cnt?）工程的?TL电路图5.2 ?脚?置和下载 5?引脚锁定S B HI S BLUFPGA/CPLD 目标芯片PIO15-PIO6严207斤PI015 PI014采 5 OD4 CPIO13 P1012 PI011?D3 QO2 QD1 PI0W 卜 109PIO6、PIO19-PIO16PIO

20、23-P(O20PIO27-PIO24PIO31-PIO2SPIO35-PIO32PIO3PIO36PIO43PIO4QPIO47-PIO44PI07PI06PI05PI04PI03PIO；PI01PIOD1 丁|_T_r_T-T_T工丄I工LL工工键8键645键4|瞎3*2键1DIG銀;沌咱NO 5图5-22 GW48实验系统模式5实验电路图图5-22 GW48实验系统模式5实验电路图|10LocatiorlK)8arkI/O StandardGene<<nw»图 5? Assignment Editor编辑器U104E>e可 CdtCGcry;Thic :gI

21、spa:tba ph 2ms tc uJ-idi you 屮dnt to n却e ai acnTmcd：.常三凸 MinC.-7:i. I ?MEWTL耳Qpn ©ien?a = :feckatmt>pJ"Ml-Z'-i10yC StaTiarzJilTLLV1TLlwitiJ«1RMTLAITLNaiwl. j»二_ 2QJCbxauonPM 9：PNJ5PB.ir：iTop Vie aKuril IWire Bon*上ispm/PITJ_53a 址胁CCJl； 仃1心3閣 MJ I国 CUT 4 0丽CW胸图5-2?两种引脚锁定对话框5

22、?2配置文件下?Mode:Progress：ErafaleISP (ChecksumU$«icMe晶 Hrdwaie Setup.DeviceCNTID.arfEP2C5FFFFFFFF_图5-25?选择编程下载文？Hard-are Settinp JTWJ 弘ttingwStitcl« progiarMning hdr站“e申 to ust when piogranYnng device This piogFantmingKsde setup applie$ on to the curent piogiwfw winMm.Cinenti sele

23、cted hdtdwas B/eBlaslerMV |LPTi Avahble hardware hemsAdd HiardwweHaidware图5-26加入编程下载方式Hardvare SetupHardware S«ttingE JTWJ Settin65Select a proflramrning hardware $etup to use when progrnirning devices. Thij progrmmirig 帕曲恥 setup applies only to the cunenl programmer wirtdow.Cuiren(l>j selec

24、ted hrdwai ec| ByteBlasterMV LPT 1)5$ LocalLPT1Available hardware items:HardwareBeGlasfeiMVno图5-27双击选中的编程方式名Mode:Progre:嚣 Hardware Setupi.Enable real-time ISP to allow background programming (for MAX II devices)FileC NTIOsofDeviceChecksumEP2C55-28 ByteBiaSterl?编程下载窗5？3 A?模式编程配置器件Mode: |

25、Active Senal Progranmng Ptujes?'I H aid阳阳 5则二| Befllwledl LPT1 Enable real-lme ISP to alow bAckugrounid proganmng (Fa MAX II deviceslFileDevceChecksuntUnicodeRi期泅ConliguieVaijBirk- CheckExanne CHTlOlinfEPCS101588 &41OOOdOOO回LPage.OQSelect DevicesDevice eanoe：acexik71 ALTERA APEX II riAPEX20K

26、.IAPEX20KE APEX20KEUASC devtcesI CFl devicesICvcIoneHCyclonBll embedded_phocessofiI Enkane«d ConfigifDevicas 1EPC1 EPC2lEXCALieUR_ARM IFL£X1OKILI 口 rvirifAEP2C20nEP2C20F256 C：EP2C2OF404 E：EP2C20a2W JEP2C35EP2C3SF4B4 LJEP2C35F672 1IEP2C35U4S4 :EP2C50 EPXSCF4&4 EP2C50F672Eri'C jOUK-i

27、 EF2C5:EP2C5F25S 口 EP2C5Q208ER2C5T1+4FPTTTn图5-29 Bymaster ?妾口 AS模式编程窗口524 J?AG间接模式编程配置器件Device family图5?选择目标器件EPSC5T14?Fiipvparriffnng He 猪Pil«7«r kA|Prop«rti«i.£ FlLvwd«tLirmq 电日 so? d.l>I npur 1iIb« to convanH«3z ITi<rCanedGerrtTdle-图5-31?选定SO?文件后？选择文件

28、压缩100XX HwdwawSsiijpi. 6eBl®l0iMVLPTlMods:* ftajew:Enable reai-lime ISP to How bdckgreuid ptograming 抽 hWX II devics|FieDeviceChetkEumUaroodeRograni/ConfigLieBioCheckEmi网帥tJSL r -.H cri10b_file.iicEP2C50IXW83FfffffFFlepcsi000幽 Auto Defect图5-32用J?AG模式对配置器件EPCS1进行间接编程5.2.5 USB Blas?编程配置器件使？方法图5-3

29、3安装USB驱动程序吕 Haidware Setup.Mode:Progress;US8-Be( USB OJTAG囲 Starr鼻 Stop图5-34设置JTag 硬件功能JTA6 Cham ConAguratkn J TAG reati住|USB-Glastei |USA4)*Sh4).(?r£P2C510»<02061 ODDIH adware.Device：Fie；m 0 roml?V - Q : p :7 2 55 2 F3 A F6 1 E7 1 Ec D 1 7 o E9 8 9 BOD6 4 F9 o匚 2 15 A o c E o A A o E A

30、 Q £ BOA 5 12 c o A F 4 6 c o 99 8 9 dob ElOD兀 9 3 0 E 1 7 FAS El 69 B B F F 2 4 F c 5 o EFIJ 4 F E o s c4 3 F F B B 9 F 4 2 F0000000000140财2日00QO3C图 5?5 在 ln?yStem Me?0ry Conte徹 Editor 中使用 USB BlaS?r5.3 ?入式?辑分析仪使法1打开S?gna?Tap ?编辑窗？InstriM MInstance%J! D j |l的出dJTAficiM时jatan国 xStatinIncimenkl

31、Comped劃 <Mg sigFMiap QRgtrifYwigi厂1<JJI>JTAfi Chari CM帀uraiAn.D-evite» SDF Marger&d4up.ScsnUumhlod«hiGverrwrrcalWlniUI PmitRd u4eOutUKk rraKIr:k 1d -9<dd nodes:Allw 411 ChDdiji “亠 Q J Auld?-Ekck:Sampk-de0lfi荷 Ako 广 Manjai|7a 二tc：MHachv DiLpi*匡|Enilt qi_0图 5-36 S?n?Tap I f编辑

32、窗2.调入待测信号3. Sign?Tap II参数设置Desgri LniscntsSionl UTitOLraiim:Lock mocfe占AUw dJ. ch:ircular:严Pre tncqei pDsticn egiT riggwI merged:Tiggior levels.kndnr： elloDfltad：kndnr： elloDfltad：11 crarc 】isploy;* Tiqgei irn Scarce: |tNAiJ.oPeri： f Rishc FdgpD«aLgt SiIM biihLSI ortB图 5-3?SignalT ap?l 编辑窗?文件存盘

33、Sett in® s - CHT1DC-ategmy:GeneralFdeiUser LtMane (|CuFert: RoiBciDevice*1 Tirrvig Anais Settings+I EDA I wl $ *bngs刃 Compi-abohStuingf日 Anatii t SyHhep$ 5eHr»af VHDL 心Viiag HDLJnpur Dai曲 F&nmetMSjndwtn Ndftst 口 plinizanrks d Filer Ss&ttrqjPhysical EfUhesis OpbnnizatiQns- its«

34、fnblwDgj=agn 合呂辭taMSiqndTtw II Loqig AiizimSpecify carr$Ddalian options lor tfe 5«gnalTap ill Logic Anazet.两 Inabis Signal? ap II Lofpc Andeer鈍聞辛II Fie nwtH： 任而不-“ 即jtcmahc 超占 Iufh on Smart compiainn f iraBmerrial routing 惟 used n I he SignalT ap II Fie. If Smart comp tat dti is turned mP frie

35、Compiler use$ rnwe disk 即bo勺就i 白daAa Khan can ncrfrase ihe spaed of incremenld roiAingLock Anak1 羽Irsfoce图5-3?设定S?gnal?ap ?与工程一同综合适配5.编译下载？ 6.启动Sig?Tap II进行采样与分析bistjic*恤耐卑q卜dBR 喇pbacqii 冃©XJIMjChanConfigudim:Sti'utncenenial Gi jJd'TiM-ntry 1?16寸11 utsNd luinrgr351 cek范漏II血卵E刚闽曲LP门*Setu

36、p.油DarDm： EP亦取翩61皿KI工| S3F Maiwgsi 占 0 |CNH0to口Instance Menagei:回 Readtoacqiiie囲XInstance石扫LtsIncfEniental Campilatian |LEs 351Mernorji- 921GM剽 cnhNDtruiiing厂351 ce)Ie9216血DI<1u,1l>lJ1AG Chsin Ccrfguraton J TAG ieatDevice:J 50F Manager 色 iJ |CNTfD.solHaidwcfe: | BpIeBldsteriMV |LF'T1 1:EP3

37、Z5b£20Ei1lDD)'Tlog 20E&D5/271Q5513 相click to insert tire barType AliasHameCOU7H-OQ而艾!I7880 B2 848688®92949698100 ICQ 1D410B1081,二二二二二二二二二二二二二二二二口二二二二二二二二二二口匚二二二二二®B®(6hXE(lDS®M®3IEX5hX5h)®E®SO3!D®SE®E®®<ZhXE(lD5图5-4?Sig?alTa?ll采样

38、已被启动7. ?gnalT和？1的其他设置和控制方法图5-39下载cn?0.sof并准备启动Signal ?ap?lIn&lance Monogcn 恢 标）因 Rcaz1 Io acqure国IXJTAG Dior Canfiguroliori： JTAG rcac1囹IntlanDBStatus| Incieirvental ComplalioriLEs: 351 |Memory: 921GMHsfdwdie: BjjteBlBaeiMVLPIl|Selup.Device1: EF2C5 KMJ20B10DDI Scan Chari?> SOFMaiagei:邑 0 CNTI

39、OlEcf口團 cnkNol runring厂261 cels921G hte01< 1IJI .”1湄log: 200B/10E/2711:00:13 riOTypeAinaN«me6472808B9610411212012B1361411521601ES1761siiii iiii i i i11i i iiii iiii i 11 iiii iii11 i i i ii ii iiii iiii i 11 iiii11i i i i ii iiii i i i iiiii i i iiii i i OOLfTnnnnnnnnnnnn-CQCQ3nnnnnnnnn ni n

40、 &CQ2rnrnrnrnrnrnriLLrn l_-lrEmrTroTmrTmrTmrTmrTmrTmrTmrTmnrmrirr匚Cl0owiruwuwuwimnruuwimnjwmnrwwmjmruiJwiJwwuwwwmmmjwLIB- CQI图5?4l Signal Tfep II数据窗设置后的信号波形?原理图输入?十方? 54 ?设计流程1. "为本项工程设计建立文件夹假设本项设计的文件夹取？为adder，路径为？d:adder ?2. 输入设计项目和存盘图5?直元件输入对话框？3将设计项目设置成可调用的元件IpLjgtiB BE - j：/tdh.'Dk&

41、gt;:k I s Ifhckl - L.dDDEfl/h adider.bdrll图5-4?将所需元件全部调入原理图编辑窗并连接好4.设计全加器顶层文件图5-44连接好的全加器原理图f adder.bdf ?将设计项目设置成工程和时序仿真PrujcLl Wi-drd: Dird-turryi. Ndiiwh arKfl Tup-Lie1*巴I Eiitily fp-due 1 ufWho.t i 轧 th.fidirIhk £Thi-s dlir«etdry willcond«si cn fils uid cth«r»d fil«s

42、 «i5X«>Ei <t«d wi th lh.i aprfl'Jt-Gt.Xf y*叩*u tyy* directory ncp>« th鼻七nvt 事丨£ Quvtui IX|D：LADDER1 二一 1Wh.it i s- th« rt«m« of tha 3 E.ro j<ct7 Lb* pjfdji亡tr taj"l*val Anti ty.1 f you wi xh,. yon c*n ux« th« rtwi« ofO 込.tht

43、 is. tlh.« tliuti « of th.* iop-l #v*li ty i ri. y-o-wr pr sji*-c-t7! Enli ly tlM4£.arc C4.se sensitive., io the c*pi t«li zation must ttsc.<:tly match that of|f*dd*rJ图5-45 ?_adder. ?jf工程设置窗New Project Wizard: Add Files page 2 of 6Select the： desi.71 files and software source

44、files you want to include in your project. Click Add All to add all desi files and software Nate' i t i e optional to add files here unless you. have desigji files not contained in the project directory or files in which the file name isFile najreType£_adder. bdfElock .hadder. bdfElock 图5?1

45、6?加入本工程所有文件()皿 S.1 Hi 10.翠 us U.K ns竇触也 <S6 ns 4fi.0fl ns1 1 1LrELtin11bin1cinsaui-1皿1_1L图5-4醉加器工程f_a ?der的仿真波形5.4.2应用宏模块的原理图设计1.计数器设计3WDT二图?-4?含有时钟使能的两位十进制计数器ya|2啦4.061 恥8.010.0MSQrFhiclk iclr ienb 初q【3.0 窃q7. coulo rH7H20° 了丨丫 2 r图5-4 ?两位十进制计数器工作波形2.频率计主结构电路设计图5-50两位十进制频率计顶层设计 原理图文件图5?51两位

46、十进制频率计测频仿真波形3.时序控制电路设计54iclk -eT (M-ENOL0CK-t>CLR5 _G_GHAAAAAA艸询T斗、CNT_ENWlfiT图5-52 ?测频时序控制电路图5-53测频时序控制电路工作波形4.顶层电路设计q(0 qi_ ILLq3Jq4q5q6q【"LOCK.CI_Rcon t er-OCLRFJN:和*.事CHT _EHCLK QC7.e 4£3. .aq3, QDIQI02Q2D3Q3D4Q4MosD6Q60?07B808OENCLK74374OCTAL D-FFCOUTARBONB0AcOBDocRON0DBNELThlOF067

47、4246BCD TO 7SEG3*L【M 二 L丄LG四2 L4USL6A e cRBONQA0B0OCRBrl00BIN0ELINOF0G74246H0)HlH2H3日4H5 miBCD TO 7SEG图5-55®率计工作时序波形5-1.靠纳？用Quar?sl ?进行vHL文本输入设计的流程：从文件输入一直到Signa?T?ll 测试。？?2.由图5-? 5-41，详细说明工程设计cnt?勺硬件工作情况？?3如何为设计？的Sign?Ta?Il加入独立采用时钟？试给出完整的程？和对? 的实测结果。？5?4.参考Qu?us II的H?p，详细说明AssSgnments ?单中Setti

48、n ?对话框的功 能。?(1?说明其中的?mi ? Re?ire mnt?& Qp?0 ?的功能、使？方法和检测途径。 ? ? 说明其中的Compilation?ocess的功能？使用方法。(?说明Analy?s ? Syr?iesi? Se?ng ?功能和使用方法，以及其中的Synthe?Netlis ?Optimiza ?0n的功能和使用方法(4)说明 F?tter Se ?i?gs中的 D?i ? Assi?Sta ?和Si?lat ?功能？举例说明它？们的使？方法。5-? ?既述Assig ?ents菜单中Aaignment Editor的功能？举例说明。5-? ?用74148

49、和与非门实现8421BCD优先编码器？用3片7伞39组成一个5- %线译码5-?歸74283加法器和逻辑门设计实现一位8421BC码加法器电路，输入输出均是 BC码，C为低位的进位信号？C(为高位的进位信号，输入为两个1位十进制数？， 输出用S表示。?8?设计一个7人表决电路，参加表决者？人，同意为1,不同意为0同意者过半 则表决通过，绿指示灯亮；表决不通过则红指示灯亮。5-?设计一个周期性产生二进制序列0?)010?100?勺序列发生器，用移位寄存器 或用同步时序电路实现，并用时序仿真器验证其功能。5-10.用？触发器构成按循环码?boo->oo?)11->1?1-?101-&g

50、t;?)0-?)00)规律工作的六进制同步计数器。?1 ?应用4位全加器和74374构成4位二进制加法计数器。5-12.用？4194、742? D触发器等器件组成8位串入并出的转换电路，要求在转 换过程中数据不变？只有当8位一组数据全部转换结束后，输出才变化一次？ 如果使用7429? 74373、触发器和非门来完成上述 功能，应该有怎样的电路？5-13. ?用 一片74163和两片？4138构成一个具有12路脉冲输出的数据分配器？要求在原理图上标明第1路到第？2路输出的位置。若改用一片74195弋替以上的 74163,试完成同样的设计。？?14.用同步时序电路对串行二进制输入进行奇偶校验，每检

51、测5位输入？输出一 个结果。当？位输入中1的数目为奇数时，在最后一位的时刻输出1。？?15.用7490设计模为872的计数器，且输出的个位？十位、百位都应符合？421码 权重？5?16.用？416?设计一个？7分频电路，用置？和置数两种方法实现。5-17?某通信接收机的同步信号为巴克码1110010。设计一个检测器，其输入为串 行码输出为检测结果y?当检测到巴克码时，输出1。5-1.哲合电路的设计(?1)实验目的：熟悉Quart US?的VHD文本设计流程全过程，学习简单组合电路的 设计、多层次电路设计、仿真和硬件测试。(2) ?实佥内容1：首先利用QuartuS H完成2选1多路选择器(例4-3 ?的文本编辑输 入(mUx21a.?h?和仿真测试等步骤，给出图4