全自动电梯控制电路

1、全自动电梯控制电路1 选题目的随着我国经济持续增长、城镇化建设的加速和房地产行业的进一步发展，对电梯的需求越来越大。所以电梯控制器就需要大强度的发展，来满足社会的需求。电梯的发展更加的智能化，节约化。对社会的发展，人民生活水平的提高具有很大的意义。所以加大对电梯控制器的发展，和技术上的研究是很重要的。随着EDA技术发展和应用领域的扩大与深入，EDA技术在电子信息、通讯、自动控制及计算机应用等领域的重要性突出。随着技术市场与人才市场对EDA的需求不断提高，产品的市场需求和技术市场的要求也必然会反映到教学领域和科研领域中来。EDA技术的提高，促进了电梯控制器的发展。电梯行业也随着科技的发展，不断地

2、出现在人们生活的各个场所，因此，对电梯控制器的设计是一个很实用的例子，对掌握EDA技术的应用也有很大的帮助。二设计目标掌握EDA设计的一般方法；熟悉Quartus 9.0软件，利用其设计一个符合以下设计要求的全自动电梯控制电路。 ·设计要求设计一个层楼房全自动电梯控制电路，其功能如下： 每层楼电梯入口处设有上，下请求开关各，电梯内设有乘客到达层次的停站要求开关。 有电梯所处位置指示装置和电梯上行，下行状态批示装置。 电梯每秒升（降）一层楼。到达某一层楼时，指示该层次的灯发光，并一直保持到电梯到达新一层为止。 电梯到达有停站请求的楼层后，该层次的指示灯亮，经过.5S，电梯门自动打开，开

3、门指示灯亮，开门5S后，电梯门自动关闭（开门指示灯灭），电梯继续运行。 能记忆电梯内外的所有请求信号，并按照电梯运行规则次第响应，每个请求信号保留至执行后撤除。 电梯运行规则，电梯处于上升模式时，只响应比电梯所在位置高的层次的上楼请求信号，由下而上逐个执行，直到最后一个请示执行完毕。如更高层次有下楼请求，则直接升到有下楼请求的楼层接客，然后便进入下降模式。电梯处于下降模式时与之相反，仅响应比电梯所在位置低的楼层的下楼请求。电梯执行完所有的请求后，应停在最后所在的位置不变，等待新的请求。 开机（接通电源）时，电梯应停留在一楼，而各种上，下请求皆被清除。 3 实现方案3.1控制器的控制模块控制器包

4、括主控制器、楼层选择器、状态显示器、译码器和楼层显示器等6个模块。乘客在电梯中选择所要到达的楼层，通过主控制器的处理，电梯开始运行，状态显示器显示电梯的运行状态，电梯所在楼层数通过译码器译码从而在楼层显示器中显示。分控制器把有效的请求传给主控制器进行处理，同时显示电梯的运行状态和电梯所在楼层数。 分控制器楼层选择器状态显示器主控制器译码器楼层显示器3.2 控制器的流程图初始化外部按键否请求信号寄存器是否有请求？楼层检测电梯运行等待判定电梯运行方向目标层与本层是否同层？是状态寄存器是内部软件执行机构否外部硬件执行机构 总流程图否是否目标层？是电梯停止开门关门否是否停止运行？是停止 电梯控制主流程

5、图 3.3控制器的VHDL描述模块流程四层电梯控制器的设计主要是对实体和结构体的设计，它的VHDL描述模块流程如图：元件库的说明端口定义实体状态机进程结构体按键信号灯信号灯控制进程结束四层电梯控制器的VHDL描述模块流程4 设计过程4.1设计程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yxh isport(clk:in std_logic; clkout:out std_logic);end yxh;architecture one of yxh issignal count

6、: std_logic_vector(8 downto 0);begin process beginwait until clk'event and clk='1' if count<500 then count<=count+1; clkout<='0' else count<=(others=>'0'); clkout<='1' end if;end process;end architecture one;Elevator模块（控制器）：library ieee;use ieee.

7、std_logic_1164.all;use ieee.std_logic_unsigned.all; entity elevator is port( clk: in std_logic; up1,up2,up3,stop1,stop2,stop3,stop4,down4,down3,down2: in std_logic; ddelay,dclose: in std_logic; upled,downled: out std_logic; floorled,nowfloor: out std_logic_vector(3 downto 0); dopenled: out std_logic

8、_vector(5 downto 0);end elevator;architecture bhv of elevator is type state_type is (start,run,opendoor,dopenwait2,dopenwait3,dopenwait4,dopenwait5,dopenwait6,dopenwait7,dopenwait8,dopenwait9,dopenwait10,dclse,up,down,upwait1,upwait2,downwait1,downwait2,stop); signal state : state_type; signal upm,d

9、ownm,stopm,dat: std_logic_vector(3 downto 0); signal dclosem,ddelaym: std_logic;beginstate_trans:process (clk,up1,up2,up3,down4,down3,down2,stop1,stop2,stop3,stop4,upm,downm,stopm,dat,ddelay,dclose)variable position: integer range 0 to 4;begin if rising_edge(clk) then if up1='1' then upm(0)&

10、lt;='1' end if; if up2='1' then upm(1)<='1' end if; if up3='1' then upm(2)<='1' end if; upm(3)<='0' if down4='1' then downm(3)<='1' end if; if down3='1' then downm(2)<='1' end if; if down2='1' then

11、 downm(1)<='1' end if; downm(0)<='0' if stop1='1' then stopm(0)<='1' end if; if stop2='1' then stopm(1)<='1' end if; if stop3='1' then stopm(2)<='1' end if; if stop4='1' then stopm(3)<='1' end if; if dc

12、lose='1' then dclosem<='1' end if; if ddelay='1' then ddelaym<='1' end if; dat<= upm or downm or stopm; case state iswhen start => if dat="0000" then state <= start; elsif position= 0 then position:=position+1; state <= run; end if;when run

13、 => if stopm(0)='1' or upm(0)='1' then stopm(0)<='0' upm(0)<='0' state<= opendoor; elsif dat> "0001" then state<= up; end if; elsif position=2 then if stopm(1)='1' or upm(1)='1' or downm(1)='1' then stopm(1)<='

14、;0' upm(1)<='0' downm(1)<='0' state<= opendoor; elsif dat> "0011" then state<= up; elsif dat< "0010" then state<= down; end if; elsif position=3 then if stopm(2)='1' or upm(2)='1' or downm(2)='1' then stopm(2)<=&

15、#39;0' upm(2)<='0' downm(2)<='0' state<= opendoor; elsif dat> "0111" then state<= up; elsif dat< "0100" then state<= down; end if; elsif position=4 then if stopm(3)='1' or downm(3)='1' then stopm(3)<='0' downm(3)

16、<='0' state<= opendoor; elsif dat< "1000" then state<= down; end if; end if; when up => upled<='1' state<=upwait1; when upwait1=> state<= upwait2;when upwait2=> upled<='0' position:=position+1; if position=2 and (upm>"0011&qu

17、ot; or stopm>"0011") and stopm(1)='0' and upm(1)='0' then state<= up; elsif position=3 and dat>"0111" and stopm(2)='0' and upm(2)='0' then state<= up; else state<= opendoor; end if;when down=> downled<= '1' state<= d

18、ownwait1; when downwait1=> state<= downwait2;when downwait2=> downled<= '0' position:=position-1; if position=3 and (downm<"0100" or stopm<"0100") and stopm(2)='0' and downm(2)='0' then state<= down; elsif position=2 and dat<"0

19、010" and stopm(1)='0' and downm(1)='0' then state<= down; else state<= opendoor; end if;when opendoor=> if position=1 then stopm(0)<='0' upm(0)<='0' elsif position=2 then stopm(1)<='0' upm(1)<='0' downm(1)<='0' elsi

20、f position=3 then stopm(2)<='0' upm(2)<='0' downm(2)<='0' elsif position=4 then stopm(3)<='0' downm(3)<='0' end if; dopenled<="001100" if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1&#

21、39; then state<= opendoor; ddelaym<='0' else state<= dopenwait2; end if;when dopenwait2=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dopenwait3; end if;when

22、 dopenwait3=> dopenled<="011110" state<= dopenwait4; when dopenwait4=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dopenwait5; end if;when dopenwait5=>

23、dopenled<="111111" state<= dopenwait6; when dopenwait6=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dopenwait7; end if;when dopenwait7=> dopenled<=&quo

24、t;011110" state<= dopenwait8;when dopenwait8=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dopenwait9; end if;when dopenwait9=> dopenled<="001100" sta

25、te<= dopenwait10; when dopenwait10=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dclse; end if;when dclse=> dopenled<="000000" if dat>"0000" t

26、hen state<= run; else state<= stop; end if;when stop => if dat>"0000" then state<= run; elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= stop; end if; end case; end if;if position=1 then nowfloor<="0001" floorled<=&q

27、uot;0001" elsif position=2 then nowfloor<="0010" floorled<="0010" elsif position=3 then nowfloor<="0011" floorled<="0100" elsif position=4 then nowfloor<="0100" floorled<="1000" else nowfloor<="0000" floo

28、rled<="0000" end if; end process state_trans;end bhv;综合实现模块：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity finalctrol is port( clk: in std_logic; up1,up2,up3,stop1,stop2,stop3,stop4,down4,down3,down2: in std_logic; ddelay,dclose: in std_logic; upled,downled: out std_logic; floorled,nowfloor: out std_logic_vector(3 downto 0); dopenled: out std_logic_vector(5 downto 0);end finalctrol;