四位全加器的VHDL设计

1、一位全加器真值表一位全加器真值表一位全加器的逻辑表达式S=A B CinCo=AB+BCin+ACin其中A,B为要相加的数，Cin为进位输 入；S为和，Co是进位输出；Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity fulladder IsPort(Ci,a,b : IN std_logic; s,Co : OUT std_logic);End fulladder;Architecture m1 Of fulladder IsSignal tmp: std_logic_vector

2、(1 downto 0);Begin tmp=(0 & a) + b + Ci; s=tmp(0); Co=tmp(1);End m1;一位全加器的数据流（逻辑）描述Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity fulladder isPort (A,B,CI:in std_logic; S,CO:out std_logic);End fulladder;Architecture dataflow of fulladder isBeginS= CI xor A xor B;

3、CO= (A and B) or (CI and A) or (CI and B);End dataflow;一位全加器的行为描述Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity fulladder is Port (a,b,cin: In bit; sum,cout: Out bit);End fulladder;Architecture behave Of fulladder IsBegin Process (a, b, cin) Begin If(a Or b Or cin)=

4、0 Then sum =0; cout =0; Elsif (a AND b AND cin ) =1 Then sum =1; cout =1; Elsif (a XOR b XOR cin ) =0 Then sum =0; cout =1; Else sum =1; cout =0; End If; End Process;End behave;4位全加器的设计，先设计4个1位的全加器，然后将低位的进位输出与高位的进位输入相连，将要进行加法运算的两个4位数的每一位分别作为每一个1位全加器的输入，进行加法运算，所有的1位全加器的输出组成一个4位数，即输入的两个4位数之和，最高位的全加器产生

5、的进位输出即两个4位数求和的进位输出。（如图）Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity adder4 IsPort(Cin : IN std_logic; x, y : IN std_logic_vector(3 downto 0); sum : OUT std_logic_vector(3 downto 0); Cout : OUT std_logic);End adder4;Architecture ax Of adder4 Is Signal c: std_logic_v

6、ector(0 to 4); Component fulladder Port(Ci,a,b : IN std_logic; s, Co : OUT std_logic); End component;Begin c(0)c(0),a=x(0),b=y(0), s=sum(0),Co=c(1); U 2 : f u l l a d d e r P o r t Map(c(1),x(1),y(1),sum(1),c(2); U 3 : f u l l a d d e r P o r t Map(c(2),x(2),y(2),sum(2),c(3); U 4 : f u l l a d d e r

7、 P o r t Map(c(3),x(3),y(3),sum(3),c(4); Cout=c(4);End ax;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4bit is port(cin: in std_logic; a,b: in std_logic_vector(3 downto 0); s: out std_logic_vector(3 downto 0); cout: out std_logic );end adder4bit;architecture beh of adder4bit is signal sint: std_logic_vector(4 downto 0); signal aa,bb: std_logic_vector(4 downto 0);begin aa=0 &