数字电路英文版第九单元PPT课件

1、Asynchronous counter ( 异步计数器 ) Cascade ( 串级 ) Decade ( 十进制 ) Decade counter ( 十进制计数器 )Recycle ( 循环 ) Ripple counter ( 纹波计数器 ) Sequence ( 时序 ) Sequential circuit (时序电路 )State diagram ( 状态图 ) State machine ( 状态机 )Synchronous counter ( 同步计数器 ) Truncated ( 截断 )Truncated sequence ( 无关态 ) Up/Down counter

2、( 加减计数器 ) 第1页/共123页KEY TERMS Asynchronous counter A type of counter in which each stage is clocked from the output of the preceding stage. Cascade To connect “end-to-end” as when several counters are connected from the terminal count output of one counter to the enable input of the next counter.第2页/

3、共123页 Decade Characterized by ten states or values. Decade counter A digital counter having ten states. Recycle To undergo transition from the final or terminal state back to the initial state. Ripple counter An asynchronous counter.第3页/共123页 Sequence The order in which several things occur in a spe

4、cified time relationship. Sequential circuit A digital circuit whose logic states follow on a specified time sequence. State diagram A graphic depicition of a sequence of states or values.第4页/共123页 State machine A logic system exhibiting a sequence of states conditioned by internal logic and externa

5、l inputs; any sequential circuit exhibiting a specified sequence of states. Terminal count The final state in a counters sequence.第5页/共123页 Synchronous counter A type of counter in which each stage is clocked by the same pulse. Truncated Shortened. Truncated sequence A sequence that does not include

6、 all of the possible states of a counter.第6页/共123页 Up/Down counter A counter that can progress in either direction through a certain sequence.第7页/共123页The term asynchronous refers to events that do not have a fixed time relationship with each other and, generally, do not occur at the same time. An a

7、synchronous counter is one in which the FF within the counter do not change states at exactly the same time because they do not have a common clock pulse.2.第8页/共123页 A 2-Bit Asynchronous Binary CounterJ0K0Q0CHIGHCLK2134Q0J1K1Q1CQ1Q0CLKQ03.第9页/共123页Clock Pulse Q1 Q0 Initially 0 0 1 0 1 2 1 0 3 1 1 4

8、0 0 Binary state sequence for the counter in Figure above.4.第10页/共123页 A 2-Bit Asynchronous Binary CounterJ0K0Q0CHIGHCLK2134Q0J1K1Q1CQ1CLKQ0第11页/共123页 A 2-Bit Asynchronous Binary CounterJ0K0Q0CHIGHCLK2134Q0J1K1Q1CQ1CLKQ0第12页/共123页Clock Pulse Q1 Q0 Initially 0 0 1 1 1 2 1 0 3 0 1 4 0 0 Binary state s

9、equence for the counter in Figure above.第13页/共123页A 3-Bit Asynchronous Binary CounterClock Pulse Q2 Q1 Q0 Initially 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0Binary state sequence for a 3-bit binary counter. 5 1 0 1 6 1 1 0 7 1 1 1 8 (recycle) 0 0 05.第14页/共123页J0K0Q0CJ1K1Q1CQ0HIGHJ2K2Q2CQ1FF2FF1FF01CLKQ0

10、Q1Q21111011111110000000000000012345678CLK6.第15页/共123页J0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0EXAMPLE 9-1 A four-bit asynchronous binary counter is shown in as follow:Q2J3K3CQ3FF3CLKHIGH第16页/共123页CLKQ0Q1Q21234Q3111000000000000110010100110001111111001056789101112131415161010101111000011110011001100第17页/共123页J0K0Q

11、0CJ1K1Q1CCLRJ2K2CFF2FF1FF0Asynchronous Decade CounterQ2J3K3CQ3FF3CLR10 decoderCLKHIGH7.第18页/共123页CLKQ0Q1Q212345678910Q3CLRGlitchGlitch8.1110000000000001100101001100010111010010第19页/共123页EXAMPLE 9-2 Show how an asynchronous counter can be implemented having a modulus of twelve with a straight binary

12、sequence from 0000 through 1011.Q3 Q2 Q1 Q00 0 0 01 0 1 1 1 1 0 0RecycleNormal next state第20页/共123页J0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0Q2J3K3CQ3FF3CLR12 decoderCLKHIGH第21页/共123页J0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0Q2J3K3CQ3FF3CLR13 decoderCLKHIGHRelated problem : EXAMPLE 9 -2第22页/共123页A 4-Bit Asynchronous Binary Cou

13、nterJ0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0Q2J3K3CQ3FF3CLRCLK B (1)CLK A(14)RO(1)RO(2)(2)(3)(12)(9)(8)(11)9.第23页/共123页CCCTR DIV 16CLK ACLK BRO(1)RO(2)Q3Q2Q1Q0(a) 74LS93A connected as a modulus-16 counter10.第24页/共123页CCCTR DIV 10CLK ACLK BRO(1)RO(2)Q3Q2Q1Q0(b) 74LS93A connected as a decade counter11.第25页/共123页E

14、XAMPLE 9-3 Show how the 74LS93A can be used as a modulus 12 counter.CCCTR DIV 10CLK ACLK BRO(1)RO(2)Q3Q2Q1Q012.第26页/共123页Related Problem: modulus-13 counterCC74LS93ACLK ACLK BRO(1)RO(2)Q3Q2Q1Q013.第27页/共123页The term synchronous refers to events that have a fixed time relationship with each other. Wit

15、h respect to counter operation synchronous means that all the FF in the counter are clocked at the same time by a common clock pulse.14.第28页/共123页A 2-Bit Synchronous Binary CounterJ0K0Q0CHIGHCLK2134Q0J1K1Q1CQ1CLKQ115.第29页/共123页A 3-Bit Synchronous Binary CounterJ0K0Q0CJ1K1Q1CQ0HIGHJ2K2CQ1FF2FF1FF0Q2C

16、LK16.第30页/共123页1CLKQ0Q1Q2111101111111000000000000001234567817.第31页/共123页Clock Pulse Q2 Q1 Q0 Initially 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0Binary state sequence for a 3-bit binary counter. 5 1 0 1 6 1 1 0 7 1 1 1 8 (recycle) 0 0 018.第32页/共123页J0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0Synchronous Binary CounterQ2

17、J3K3CQ3FF3CLKHIGHQ0 Q1 Q2Q0 Q119.第33页/共123页CLKQ1Q2Q3Q0Q0Q1Q0Q1Q0Q1Q2Q0Q1Q220.第34页/共123页A 4-Bit Synchronous Decade CounterJ0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0Q2J3K3CQ3FF3HIGHCLKQ321.第35页/共123页CLKQ0Q1Q212345678910Q322.第36页/共123页Clock Pulse Q3 Q2 Q1 Q0 Initially 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0S

18、tates of a BCD decade counter 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 10 (recycles) 0 0 0 0 9 1 0 0 1 8 1 0 0 023.第37页/共123页J0 = K0 = 1, J1 = K1 = Q0Q3J2 = K2 = Q0Q1, J3 = K3 = Q0Q1Q2 + Q0Q324.第38页/共123页 An up/down counter is one that is capable of progressing in either direction through a certain sequence. A

19、n up/down counter, sometimes called a bidirectional counter, can have any specified sequence of states.25.第39页/共123页A 3-bit binary counter that advances upward through its sequence ( 0, 1, 2, 3, 4, 5, 6, 7 ) and then can be reversed so that it goes through the sequence in the opposite direction ( 7,

20、 6, 5, 4, 3, 2, 1, 0 ) is an illustration of up/down sequential operation.0, 1, 2, 3, 4, 5, 4, 3, 2, 3, 4, 5, 6, 7, 6, 5, ect.DOWNDOWNUPUP26.第40页/共123页Clock Pulse UP Q2 Q1 Q0 DOWN 0 0 0 0Up/Down sequence for a 3-bit counter. 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 127.第41页/共123页J0 = K0

21、 =1J1 = K1 = ( Q0* UP ) + (Q0 * DOWN ) J2 = K2=( Q0* Q1 *UP ) + (Q0*Q1* DOWN ) 28.第42页/共123页J0K0CJ1K1CJ2K2CQ0FF0HIGHFF1FF2Q0Q1Q1Q2Q2CLKU/DDOWNUPQ0*UPQ0*DOWN29.第43页/共123页EXAMPLE 9-4 Show the timing diagram and determine the sequence of a 4-bit synchronous binary up/down counter if the clock and UP/DO

22、WN control inputs have waveforms as shown in Fig. 9-24 ( a ). The counter starts in the all 0s state and is positive edge-triggered.第44页/共123页CLKQ1Q2Q3Q0UPDOWNDOWNUPUP/DOWN30.1000001100 1000001010000010111000100000011011100000000000Fig. 9-24 ( a )第45页/共123页Q3 Q2 Q1 Q00 0 0 00 0 0 1 0 0 1 0 0 0 1 10

23、1 0 00 0 1 10 0 1 00 0 0 10 0 0 01 1 1 10 0 0 00 0 0 10 0 1 00 0 0 10 0 0 0UPUPDOWNDOWN31.第46页/共123页Related Problem Show the timing diagram if the UP/DOWN control waveform in Figure 9-24 ( a ) is inverted. 第47页/共123页CLKQ1Q2Q3Q0UPDOWNDOWNUPUP/DOWN30.111101111010100110111111101110101000000110111011001

24、11000Fig. 9-24 ( a )0000第48页/共123页 This section is recommended for those who want an introduction to counter design or to state machine design in general.32.第49页/共123页General Model of a Sequential CircuitCombinationallogicMemoryI0I1ImY0Y1YpQ0Q1QnQ0Q1QxCLKExcitation linesState variable lines33.第50页/共

25、123页Step 1: State Diagram000110011101001010100111State diagram for a 3-bit Gray code counter.34.第51页/共123页Step 2: Next- State Table Q2 Q1 Q0 Q2 Q1 Q0 Present State Next State 0 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1 0 1 1 0 0 1 0 0 0 0 0Next-state table for 3-bit Gra

26、y code counter.35.第52页/共123页Step 3: Flip-Flop Transition Table QN QN+1 J K Output Transition Flip-Flop Input 0 0 0 XTransition table for a J-K flip-flop. 0 1 1 X 1 0 X 1 1 1 X 036.第53页/共123页Step 4: K-MAPPresent State Next StateQ2 Q1 Q0 Q2 Q1 Q0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1

27、 1 1 1 1 1 1 0 1 Output Flip-flopTransitions Inputs QN QN+1 J K 0 0 0 X 1 1 X 00001111001Q2Q1Q0K0 map0001111001Q2Q1Q0J0 map 0 0 0 0 0 1 1 0 1 1 0 0 1 0 X 1 0 1 1 X1X1X37.第54页/共123页0001111001Q2Q1Q01X0001111001Q2Q1Q0100001111001Q2Q1Q01X0001111001Q2Q1Q01X0001111001Q2Q1Q0X0001111001Q2Q1Q01X00XXXXXXX0001

28、XXX000000XXXXXXXXX100001Q1Q0Q2Q0Q1Q0Q2Q1Q2Q1Q2Q1Q2Q1Q2Q1J2 mapJ1 mapJ0 mapK2 mapK1 mapK0 map38.第55页/共123页Step 5: Logic Expression for Flip-Flop Input J0 = Q2Q1 +Q2Q1 = Q2 + Q1K0 = Q2Q1 +Q2Q1 = Q2 + Q1J1 = Q2Q0K1 = Q2Q0J2 = Q1Q0K2 = Q1Q039.第56页/共123页J0K0CJ1K1CJ2K2CQ0FF0FF1FF2Q0Q1CLKQ2Q2Q140.第57页/共123

29、页To design in another way000111100111010001Q2Q1Q2Q1Q0 mapQ2Q1Q0Q0n+1 =Q2Q1+Q2Q1 = Q2+Q1 (Q0+Q0) = Q2+Q1 Q0+Q2+Q1Q0J0=Q2+Q1 K0=Q2+Q1Qn+1 =JQn+KQn第58页/共123页0001111001Q2Q1Q011000110Q2Q0Q1 mapQ1Q0Q1n+1 =Q1Q0+Q2Q0( Q1+Q1) = Q0Q1 +Q2Q0Q1+Q2Q0Q1 = (Q0+Q2Q0)Q1+Q2Q0Q1 = Q2Q0Q1 + Q2Q0Q1J1=Q2Q0 K1=Q2Q0Qn+1 =JQ

30、n+KQn第59页/共123页0001111001Q2Q1Q010001101Q1Q0Q2 mapQ0Q2Q2n+1 =Q1Q0+Q0Q2 = Q1Q0 ( Q2+Q2) + Q0Q2 = (Q0+Q1Q0)Q2+Q1Q0Q2 = Q1Q0Q2 + Q1Q0Q2 J2=Q1Q0 K2=Q1Q0Qn+1 =JQn+KQn第60页/共123页EXAMPLE 9-5 : Use J-K FF001101010111Present State Next State 0 0 1 0 1 0Q2 Q1 Q0 Q2 Q1 Q0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 0 0 141.第6

31、1页/共123页 QN QN+1 J K Output Transition Flip-Flop Input 0 0 0 XTransition table for a J-K flip-flop. 0 1 1 X 1 0 X 1 1 1 X 042.第62页/共123页0001111001Q2Q1Q0XX0001111001Q2Q1Q0100001111001Q2Q1Q01X0001111001Q2Q1Q0XX0001111001Q2Q1Q0X0001111001Q2Q1Q01XXXXXXXXXXX10XXXX1XXX1XXXXXXXXXX0101XXQ11Q11Q21J2 mapJ1 ma

32、pJ0 mapK2 mapK1 mapK0 map43.第63页/共123页J0K0CCLKJ1K1CQ0J2K2CQ2Q1Q211J0 = 1 , K0 = Q2J1 = K1 = 1J2 = K2 = Q144.第64页/共123页To design in another way0001111001X0X111XXQ0Q2Q0Q0 mapQ2Q1Q0Q0n+1 = Q0+Q2Q0 J0=1 K0=Q2Qn+1 =JQn+KQn第65页/共123页0001111001X0X110XXQ1Q1 mapQ2Q1Q0Q1n+1 = Q1 J1=1 K1=1Qn+1 =JQn+KQn第66页/共12

33、3页0001111001X0X101XXQ2Q1Q2 mapQ2Q1Q0Q2n+1 = Q1Q2+ Q1Q2 J2= K2=Q1Qn+1 =JQn+KQnQ2Q1第67页/共123页 Counters can be connected in cascade to achieve higher-modulus operation. In essence, cascading means that the last-stage output of one counter drives the input of the next counter.45.第68页/共123页J0K0CCLKJ1K1CJ

34、2K2CJ3K3CJ4K4CQ4Q0Q1Q2Q3Modulus-4 counterModulus-8 counterTwo cascaded counters ( all J and K are HIGH ).46.第69页/共123页CTR DIV 10CTENQ0 Q1 Q2 Q3TCCCOUNTER 1CTR DIV 10CTENQ0 Q1 Q2 Q3TCCCOUNTER 2HIGHCLKfinfinfin10100A modulus-100 counter using two cascade counters.47.第70页/共123页CTR DIV 10CTENTCCHIGHCTR

35、DIV 10CTENTCCCTR DIV 10CTENTCC100 kHz10 kHz1 kHz1 MHz48.第71页/共123页CTR DIV 16ENPD3 D2 D1 D0RCOC 0 0 0 0ENTCTR DIV 16ENPD3 D2 D1 D0RCOCENTCTR DIV 16ENPD3 D2 D1 D0RCOCENTCTR DIV 16ENPD3 D2 D1 D0RCOCENT 1 1 0 0 0 0 1 1 0 1 1 0016C16316616CLKLOADMSDLSDOutput49.第72页/共123页216 = 65,536( 63C0 )16 = 6*163 + 3

36、 *162 +12*16 = 25,53665,536 25,536 = 40,00050.第73页/共123页 In many applications, it is necessary that some or all of the counter states be decoded. The decoding of a counter involves using decoders or logic gates to determine when the counter is in a certain binary state in its sequence. For in stance

37、, the terminal count function previously discussed is a single decoded state in the counter sequence.51.第74页/共123页J0K0CJ1K1CJ2K2CQ0Q0Q1Q2CLKHIGHLSBMSBDecoded 6 Q0Q2Q111152.第75页/共123页EXAMPLE 9-9 Decoding 2 and 7J0K0CJ1K1CJ2K2CQ0Q0Q1Q2LSBMSBFF0FF1FF2CLK12753.第76页/共123页1CLKQ0Q1Q211110111111100000000000

38、0001234567827Decoded output54.第77页/共123页A 3-bit Up/Down Gray Code Counter Design000110011101001010100111State diagram for a 3-bit Gray code counter.Y = 1Y = 055.第78页/共123页 Q2 Q1 Q0 Q2 Q1 Q0 Q2 Q1 Q0 Present State Next State 0 0 0 1 0 0 0 0 1 Y = 0 (DOWN) Y = 1 ( UP ) 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0

39、1 0 0 1 0 0 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 0 0 1 0 1 0 0 056.第79页/共123页 QN QN+1 J K Output Transition Flip-Flop Input 0 0 0 XTransition table for a J-K flip-flop. 0 1 1 X 1 0 X 1 1 1 X 0第80页/共123页Q2Q1Q0YQ2Q1Q0Y01X11X1111XX00000000010101011111111110101010K0 mapJ0 ma

40、pQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ0YXXXX000X1X1XXXXX0000Q2Q1Y第81页/共123页Q2Q1Q0YQ2Q1Q0YXXX000XXX0X000000000010101011111111110101010K1 mapJ1 mapQ2Q0YQ2Q1YQ2Q0YQ2Q0YQ0Y1XX00X0X01XX000XX11X第82页/共123页Q2Q1Q0YQ2Q1Q0Y1XX0X0X0001100000000010101011111111110101010K2 mapJ2 mapQ1Q0YQ1Q0YQ1Q0YQ1Q0YQ0Y00XXXX0XXX

41、XXX00X0X01第83页/共123页 QN QN+1 D Output Transition Flip-Flop Input 0 0 0Transition table for a D flip-flop. 0 1 1 1 0 0 1 1 157.第84页/共123页Q2Q1Q0YQ2Q1Q0Y111111111111111100000000010101011111111110101010D0 mapD1 mapQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ2Q0YQ1Q0Q2Q0YQ0Y58.第85页/共123页Q2Q111111110000010111111010D2 mapQ1Q0YQ2

42、Q0Q1Q0Y1Q0Y59.第86页/共123页The Boolean Expressions for the D InputsD0 = Q2Q1Y + Q2Q1Y + Q2Q1Y + Q2Q1YD1 = Q2Q0Y + Q2Q0Y + Q1Q0D2 = Q1Q0Y + Q1Q0Y + Q2Q0Logic diagram of the 3-bit up/down Gray code counter in page 584 Figure 11-13. 60.第87页/共123页 Design problem 2 - sequence detector Consider a synchronous

43、 sequential logic circuit that will detect a defined serial pattern appearing on a signal data input. Suppose the serial input to detect is 0110011, with Z becoming a 1 immediately after the last bit appears in the sequence.第88页/共123页 Design procedure 1. Derive the state diagram. 2. Draw the state t

44、able. 3. Assign state variable patterns to states. 4. Draw the assigned state table. 5. Derive the flip-flop input functions, and in our design. 6. Derive the output function of a K-map, and finally. 7. Draw the logic circuit.第89页/共123页1/02/03/04/05/06/07/08/10110010010001111State diagram 0110011Sta

45、te numberOutput Z第90页/共123页1/02/03/04/05/06/07/08/1011001001000111State diagram 0110110011State numberOutput Z第91页/共123页 State table present state Next state output x= 0 x = 1 Z 1 2 1 0 2 2 3 0 3 2 4 0 4 5 1 0 5 6 3 0 6 2 7 0 7 2 8 0 8 2 1 1第92页/共123页 State variable assignment For example: state 1 =

46、 001, state 2 = 010, state 3 = 011, state 4 = 100, state 5 = 101, state 6 = 110, state 7 = 111, state 8 = 000. There are a very large number of possible assignments and each would lead to specific next state and output functions. 第93页/共123页 Rule 1 Assign codes which differ in one variable to states

47、that lead to the same next state. ( 次态相同, 现态应相邻编码 )001011000第94页/共123页 Rule 2 Assign codes that differ in one variable for next states of a present state. (现态相同,次态应相邻编码 )100000110第95页/共123页 We make the assignment: state 1 = 000, state 2 = 111, state 3 = 101, state 4 = 001, state 5 = 010, state 6 = 1

48、10, state 7 = 011, state 8 = 100第96页/共123页 present state Next state output y3y2y1 x= 0 x = 1 Z 000 111 000 0 111 111 101 0 101 111 001 0 001 010 000 0 010 110 101 0 110 111 011 0 011 111 100 0 100 111 000 1 第97页/共123页 Flip-flop input functions The input functions for the three flip-flops are obtaine

49、d as before by mapping the next state variables in the assigned state table onto Karnaugh maps.第98页/共123页xy3xy3Q0Y11111111111100000000010101011111111110101010 xy3y2y1y2y1x y1xy3y2y1y2y1111111 Y3 Y21y3y2第99页/共123页xy3Q0Y11110000010111111010 x y2y1y3y1y2y1111 Y11y3y2y1xy2y1 Y3 = x y1 + x y3 + y2y1 +y3y

50、2 Y2 = x + y3y2 y1 Y1 = y3 y1 + y3y2y1 + x y2y1+ xy2y1 + xy2y1Output function Z = y3y2y1Draw logic circuit .11x y2y1第100页/共123页Mealy model designs The Mealy model state diagram indicates the outputs on the arcs leading to the state, together with the inputs that caused the transition to that state.

51、Often the Mealy model state diagram has less states than a Moore model state diagram for the same problem.第101页/共123页 The same design steps 1. Derive the state diagram. 2. Draw the state table. 3. Assign state variable patterns to states. 4. Draw the assigned state table. 5. Derive the flip-flop inp

52、ut functions ( on K-maps ) 6. Derive the output function of a K-map, and finally. 7. Draw the logic circuit.第102页/共123页Mealy model state diagramThe difference is that only state 8 is eliminated in Mealy model.21/0State numberOutput Z3415670/01/01/11/01/00/01/01/00/00/00/00/0Input , x0/0第103页/共123页 P

53、resent state Next state output, Z x= 0 x = 1 x= 0 x = 1 1 2 1 0 0 2 2 3 0 0 3 2 4 0 0 4 5 1 0 0 5 6 3 0 0 6 2 7 0 0 7 2 1 0 1第104页/共123页 Present state Next state Next output, Z y3y2y1 x= 0 x = 1 x= 0 x = 1 000 111 000 0 0 111 111 101 0 0 101 111 001 0 0 001 010 000 0 0 010 110 101 0 0 110 111 011 0

54、0 011 111 100 0 1 第105页/共123页xy3xy3Q0Y11X111111100000000010101011111111110101010 xy3y1xy2y1x y1xy3y2y1y2y1111X1 Y3 Y211XXy3y2y11y3y2y1第106页/共123页xy3Q0Y11110000010111111010 x y2y1y3y2y111X Y11xy2y1 Y3 = x y1 + x y3 + y3y2y1+ x y2y1 + y3y2y1 Y2 = x + y3 y1 Y1 = y3 + x y2y1+ xy2y1 + xy2y1 Output function Z =x y3y2y1Draw logic circuit .X11xy2y1 第107页/共123页 Exercise sequence 11011/02/03/04/05/1110101000State numberOutput Z1第108页/共123页 Present state Next state output, Z x= 0 x = 1 1 1 2 0 2 1 3 0 3 4 3 0 4 1 5 0 5 1 2 1 Present state Next state output, Z x= 0 x = 1 x= 0 x