电子技术基础课程设计-出租车计费系统

1、电子课设：出租车计费系统全套设计加扣 3346389411或3012250582自动化1104 出租车计费器课程设计任务及要求：能实现计费功能。计费标准为：按行驶里程收费，3公里内起步价10元，超过三公里的部分每公里2元。当汽车停止时间大于5min时超出的部分加收1元/min的等待费用。实现预置功能：能预置起步价和每公里收费。实现模拟功能：能模拟出租车启动、暂停、停止状态。设计动态扫描电路，实时显示车费。用Verilog HDL语言设计符合上述要求的出租车计价器。完成电路全部设计后，通过下载到DE0板上验证电路正确性。各模块功能如下：1、 里程计算模块通过start开关设置出租车行驶与暂停状态

2、。Start为1时出租车在行驶中，此时通过number开关提供上升沿。当number由0到1时表示出租车行驶了1km，使得里程与车费产生相应变化。2、 时间计算模块Start为0时利用时钟脉冲计时，每分钟等待时间数增加一。使得相应车费增加。3、 车费计算模块当行驶里程不超过3km时，车费为10元起步价。当里程超过3km或等待时间超过五分钟时车费相应增加。代码模块一：module distans_count(clk,start,reset,number,distansl,distansh,distans_enable);input clk,start,reset,number;output di

3、stansl,distansh,distans_enable;reg distans_enable;reg3:0 distansl,distansh;always(posedge clk)beginif(reset)begindistansl<=0;distansh<=0;distans_enable<=0;endelse if(start)beginif(number)beginif(distansl=9)begindistansl<=0;if(distansh=9)begindistansh<=0;endelse distansh<=distansh+1

4、;endelse distansl<=distansl+1;endendif(!(distansl<=2&&distansh=0)begindistans_enable<=1;endendendmodule模块二：module time_count(clk,reset,start,timel,timeh,time_enable);input clk,reset,start;output timel,timeh,time_enable;reg time_enable;reg3:0timel,timeh;reg7:0seconds;always(posedge c

5、lk)beginif(reset)begintimel,timeh<=8'h00;endelse beginif(!start)begintime_enable<=0;if(seconds<10)beginseconds<=seconds+1;endelsebegin seconds<=8'h0;if(timel=9)begintimel<=0;if(timeh=9)begintimeh<=0;endelse timeh<=timeh+1;endelse timel<=timel+1;endif(seconds=10)&am

6、p;&!(timel<2&&timeh=0)begintime_enable<=1;endendendendendmodule模块三：module select_clk(clk,reset,start,time_enable,number,select_clk);input clk,start,reset,number,time_enable;output select_clk;wire select_clk;assign select_clk=reset?clk:(start?number:time_enable);endmodule模块四：module

7、fee_count(select_clk,time_enable,distans_enable,reset,start,fee1,fee2,fee3);input select_clk,time_enable,distans_enable,reset,start;output3:0 fee1,fee2,fee3;reg3:0 fee1,fee2,fee3;always(negedge select_clk)beginif(!reset)beginif(distans_enable|time_enable)beginif(start)beginif(fee3>=8)beginfee3=fe

8、e3-8;if(fee2=9)beginfee2<=0;if(fee1=9)fee1<=0;else fee1<=fee1+1;endelse fee2<=fee2+1;endelse fee3<=fee3+2;endelsebeginif(fee3>=9)beginfee3=fee3-9;if(fee2=9)beginfee2<=0;if(fee1=9)beginfee1<=0;endelse fee1<=fee1+1;endelse fee2<=fee2+1;endelse fee3<=fee3+1;endendendels

9、e fee1,fee2,fee3<=12'h010;endendmodule模块五：module divided_Frequency(_1HZ,_50MHZ);input _50MHZ;output _1HZ;reg _1HZ;reg 24:0 count; always (posedge _50MHZ)begin if(count=24999999)begin count<=0;_1HZ<=_1HZ;endelse count<=count+1;endendmodule模块六：module Qiduanyima(segout,segin);input 3:0

10、segin;output 6:0 segout;reg 6:0 segout;always(segin)begincase(segin) /gfedcba4'b0000:segout = 7'b1000000;/0 4'b0001:segout = 7'b1111001;/14'b0010:segout = 7'b0100100;/2 4'b0011:segout = 7'b0110000;/3 4'b0100:segout = 7'b0011001;/4 4'b0101:segout = 7'b0

11、010010;/5 4'b0110:segout = 7'b0000010;/6 4'b0111:segout = 7'b1111000;/7 4'b1000:segout = 7'b0000000;/8 4'b1001:segout = 7'b0010000;/9 default:segout=7'b0100011;/#endcaseendendmodule模块七：module choose(in1,in2,in3,in4,in5,in6,in7,out1,out2,out3,out4,ch_enable,clk);input 6:0 in1,in2,in3,in4,in5,in6,in7;input clk,ch_enable;output out1,out2,out3,out4;reg6:0 out1,out2,out3,out4;alway