VHDL实验及其程序

1、2 输入与门library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity and2 is port (a, b : in std_logic; c : out std_logic); end and2; architecture abc of and2 is begin c=a and b; end abc; 2 输入或门library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity or2 is po

2、rt (a, b : in std_logic; c : out std_logic); end or2; architecture abc ofor2 is begin c=a or b; end abc; 2 输入异或门library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity nand2 is port (a, b : in std_logic; c : out std_logic); end nand2; architecture abc of nand2 is begin c=not

3、(a and b); end abc; 非门的设计library ieee; use ieee.std_logic_1164.all; entity inv is port (a : in std_logic; c: out std_logic); end inv; architecture struct of inv is begin c=not a; end struct; d 触发器的设计检测到时钟信号clk 的上升沿，把输入信号d 送给输出q library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;

4、 entity ddd is port (d, clk : in std_logic; q : out std_logic); end ddd; architecture abc of ddd is begin process(clk) begin if(clkevent and clk=1) then q=d; end if; end process; end abc; 边沿 jk 触发器设计j k qn+1 qn+1 0 0 qn qn 0 1 0 1 1 0 1 0 1 1 qn qn library ieee; use ieee.std_logic_1164.all; use ieee

5、.std_logic_arith.all; entity jk2 is port (j,k,clk : in std_logic; q : buffer std_logic); end jk2; architecture jkq of jk2 is signal qq:std_logic; begin process(clk) begin if (clkevent and clk=1) then if(j=0 and k=0) then qq=qq; elsif(j=0 and k=1) then qq=0; elsif(j=1 and k=0) then qq=1; else qq=not

6、qq; end if; end if; q=qq; end process; end jkq; 实验内容： 3 8译码器的设计。提示信息：常见的 3 8 译码器的真值表如右：当 en1 时，译码器正常工作；当en=0 时，译码器不动作。library ieee; use ieee.std_logic_1164.all; entity m38 is port(a,b,c,en:in std_logic; y:out std_logic_vector(7 downto 0); end m38; architecture d38 of m38 is signal indata:std_logic_v

7、ector(2 downto 0); begin indatayyyyyyyyy=xxxxxxxx; end case; else y=00000000; end if; end process; end d38; 用构造体的结构描述方式实现如图所示组合逻辑电路，仿真其功能并进行功能描述。library ieee; use ieee.std_logic_1164.all; entity ex2 is port (ai,bi : in std_logic; gi:out std_logic; mi,li:inout std_logic); end ex2; architecture struct

8、 of ex2 is component nand2 is port(a,b:in std_logic; c:out std_logic); end component; component inv is port(a:in std_logic; c:out std_logic); end component; signal a1,b1: std_logic; begin u1:inv port map(ai,a1); u2:inv port map(bi,b1); u3:nand2 port map(a1,bi,mi); u4:nand2 port map(ai,b1,li); u5:nan

9、d2 port map(mi,li,gi); end struct; 描述一个 7 段显示译码器逻辑（共阴极），仿真其功能。library ieee; use ieee.std_logic_1164.all; entity decode is port(q8,q4,q2,q1:in std_logic; y:out std_logic_vector(7 downto 0); end decode; architecture de of decode is signal indata:std_logic_vector(3 downto 0); begin indatayyyyyyyyyyy=00

10、000000; end case; end process; end de; 设计一个 3bits 的可逆计数器。提示信息：由名称可以知道，它的计数方式可以加（检测到clk 时钟的上升沿，计数器加1） ，也可以减（检测到 clk 时钟的上升沿，计数器减1） 。使用一个控制信号dir 决定计数器是作加法或减法的动作library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(clk,dir:in std_logic; q:out std_logic_vector

11、(2 downto 0); end counter; architecture mycount of counter is signal count3:std_logic_vector(2 downto 0); begin q=count3; process(clk,dir) begin if(clkevent and clk=1)then if(dir=1) then count3=count3+1; else count3=count3-1; end if; end if; end process; end mycount; 如下表所示为四位双向移位寄存器74ls194 的真值表， 编写程

12、序描述该逻辑，仿真其功能。 其中各端口功能说明如下：d0d3: 并行数码输入端。cr: 异步清0 端，低电平有效。sr、sl：右移、左移串行数码输入端。s1、 s0： 工作方式控制端。library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ls194 is port (cp,cr,sl,sr,so,s1: in std_logic; d: in std_logic_vector(0 to 3); q: out std_logic_vector(0 to 3); end ls194; architecture rtf of ls194 is signal reg_4: std_logic_vector(0 to 3); begin process(cr,cp) begin if(cr=0) then reg_4=0000; else if(cpevent and cp=1) then if(s1=0 and s0=1) then reg_4(0)=sr; reg_4(1)=reg_4(0); reg_4(2)=reg_4(1); reg_4(3)=reg_4(2); elsif(s1=1 and s0=0) then reg_4(0)=reg_4(1);