STM32IAP,APP参数配置,向量表映射

1、基于MDK的STM32系列IAP和APP程序的配置很多人在做IAP程序的时候，一般都能很容易就做出来，但是在做APP的时候，却经常会跑飞，其中原理，大都由于MDK配置出的问题，或者是APP没有映射向量表。向量表起始地址默认的是 0x08000000,在IAP的程序里不用再映射，但APP的起始地址已经不再是0x08000000，所以，必须要映射到实际的起始地址，否则当 IAP跳转到APP的时候， 程序直接就飞了。如我的APP起始地址是0x08005400，我的映射函数是这么配置的NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x5400); NVIC_VectT

2、ab_FLASH 的值就是 0x08000000 o下面让我们来看看IAP和APP的MDK配置，其中片子为 STM32F103RE，IAP 起始是0x08000000 ,程序大小是 0x5400字节；APP的起始地址是 0x08005400 ,程序大小 是0X7AC00，配置如下：1. IAP 的 option for target'stm3210e-evel'配置1)这里要注意的是IROM1的配置2)这里是片子的选择配置单击setting进入下面的界面这里要注意Programming Algorithm 的size大小。实际上经过测试，这个size使用片子的最大的容量也没关系

3、，即0x00080000(512K)，也不会影响程序的运行。3)以上是大家需要配置的，以下是其它的配置，与IAP功能无关紧要，是我的配置，仅供大豕参考。Options for Target rSTI3210E-EVAL,冈Options for Target rSTI3210E-EVAL,冈Device Target | Output Listing User | C/C+ | Asm Linker Debug Utilities |Select Folder for Listings.Page idth: |79Ragg Length: |66 十|V Assembler Listing:

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16、不可与IAP有区域重叠，而且size不能超过片子的大小。 这里0X7AC00与IAP的0x5400之和，刚好是 0x80000，即512KOptions for Target r STM32LDE-EFAL1冈Devi ceT虹g色t Output | Listing | User | C/C+AsmLinker Debug Vtili ti esSTMiicroelectronics STM32F103RE(MHz): 5-Opefating system; | None |SstorrtViewef File (.Sfr):I-ICode GenerationUse Cross-Modul

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18、 for algorithm(RAM 为运算法则准备的空间)的size和programming for algorithm(程序为运算准备的空间)的size都是默认的，当然程序为运算准备 的空间大小也可以改成0X7AC00，起始地址改为 0x08005400，但经过调试效果都一样。其它MDK的设置参照IAP的(3)点以下的说明要特别注意，稍不留神就会出问题。平时我们在建立工程的时候，可能不会 去重新映射向量表，原因是一般我们程序的起始地址都是默认的0x08000000，但此刻的APP的起始地址是0x08005400，那么就必须重新映射了。需要注意的是，在系统时钟配置好后， 马上就做向量映射，中

19、间最好先不要做其它的配置，比如端口初始化等等，否则程序跑飞也不一定的。下面的这段代码就是我实际的配置过程。Void Mai n( void)SystemInit();系统初始化NVIC_SetVectorTable(NVIC_V ectTab_FLASH, 0x5400);/向量表映射 void System In it (void)/*!< Set MSION bit */RCC->CR |= (ui nt32_t)0x00000100;/*!< Reset SW1:0, HPRE3:0, PPRE12:0, PPRE22:0, MCOSEL2:0 a nd MCOPRE2

20、:0 bits */RCC->CFGR &= (ui nt32_t)0x88FFC00C;/*!< Reset HSION, HSEON, CSSON and PLLON bits */RCC->CR &= (ui nt32_t)0xEEFEFFFE;/*!< Reset HSEBYP bit */RCC->CR &= (uin t32_t)0xFFFBFFFF;/*!< Reset PLLSRC, PLLMUL3:0 a nd PLLDIV1:0 bits */RCC->CFGR &= (ui nt32_t)0xFF0

21、2FFFF;/*!< Disable all in terrupts */RCC->CIR = 0x00000000;/* Con figure the System clock freque ncy, AHB/APBx prescalers and Flash sett ings */SetSysClock();/ SetSysClock65K();#ifdef VECT_TAB_SRAMSCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocati on in In ternal SRAM. */#els

22、eSCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocati on in In ternalFLASH. */#en difstatic void SetSysClock(void)_10 uin t32_t StartUpCou nter = 0, HSEStatus = 0;/* SYSCLK, HCLK, PCLK2 and PCLK1 con figurati on*/* En able HSE */RCC->CR |= (ui nt32_t)RCC_CR_HSEON);/* Wait till HS

23、E is ready and if Time out is reached exit */doHSEStatus = RCC->CR & RCC_CR_HSERDY;StartUpCou nter+; while(HSEStatus = 0) && (StartUpCo un ter != HSE_STARTUP_TIMEOUT);if (RCC->CR & RCC_CR_HSERDY) != RESET)HSEStatus = (ui nt32_t)0x01;elseHSEStatus = (ui nt32_t)0x00;if (HSEStatus

24、 = (ui nt32_t)0x01)/* En able 64-bit access */FLASH->ACR |= FLASH_ACR_ACC64;/* En able Prefetch Buffer */FLASH->ACR |= FLASH_ACR_PRFTEN;/* Flash 1 wait state */FLASH->ACR |= FLASH_ACR_LATENCY;/* Power e nable */RCC->APB1ENR |= RCC_APB1ENR_PWREN;/* Select the Voltage Ra nge 1 (1.8 V) */PWR->CR = PWR_CR_VOS_0;/* Wait Un til the V oltage Regulator is ready */while(PWR->CSR & PWR_CSR_VOSF) != RESET)/* HCLK = SYSCLK /1*/RCC->CFGR |= (ui nt32_t)RCC_CFGR_HPRE_DIV1;/* PCLK2 = HCLK /1*/RCC->CFGR |= (ui nt32_t)RCC_