选择DCDC转换器的最佳开关频率

1、Direct current-to-direct current (DC/DC) converters with faster switching frequencies are becoming popular due to their ability to decrease the size of the output capacitor and inductor to save board space. On the other hand, the demands from the point-of-load (POL) power supply increase as processo

2、r core voltage drops below 1V, making lower voltages difficult to achieve at faster frequencies due to the lower duty cycle.Many power IC suppliers are aggressively marketing faster DC/DC converters that claim to save space. A DC/DC converter switching at 1 or 2 MHz sounds like a great idea, but the

3、re is more to understand about the impact to the power supply system than size and efficiency. Several design examples will be shown revealing the benefits and obstacles when switching at faster frequencies.Selecting an ApplicationThree different power supplies were designed and built to show the tr

4、ade offs of high switching frequency. For all three designs, the input voltage is 5V, the output voltage is 1.8V, and the outputcurrent is 3A. These requirements are typical for powering a performance processor such as a DSP, ASIC or FPGA. To bound the filter design and performance expectations, the

5、 allowable ripple voltage is 20 mV , which is about one percent of the output voltage, and the peak-to-peak inductor current is chosen at 1A.Independent designs at frequencies of 350, 700, and 1600 kHz will be compared to illustrate the benefits and obstacles. The TPS54317, a 1.6 MHz, low-voltage, 3

6、 A synchronous-buck DC/DC converter with integrated MOSFETs was chosen as the regulator in each example. The TPS54317 from Texas Instruments features a programmable frequency, external compensation and is intended for high-density processor power point-of-load applications.Selecting the Inductor and

7、 CapacitorThe inductors and capacitors are chosen according to the following simplified formulas:Equation 1:V = L x di/dtRearranging: L > Vout x (1-D)/( I x Fs)where: I = 1 A peOk-peak; D = 1.8 V/5 V="0".36Equation 2:I = C x dv/dtRearranging: C > 2 x 1/(8 x Fs x V) where: V = 20 mV=

8、1 A peak-to-peakEquation 2 assumes a capacitor is used that has negligible series resistance, which is true for ceramic capacitors. Ceramic capacitors were chosen for all three designs because of their low resistance and small size. The multiplier of two shown above in the rearranged Equation 2 acco

9、unts for capacitance drop associated with DC bias, since this effect is not accounted for in the datasheets of most ceramic capacitors.The circuit in Figure 1 was used to evaluate the performance of each design on the bench.Figure 1: TPS54317 Reference Schematic.The components in the schematic that

10、do not have values are the components that were modified in each design. The output filter consists of L1 and C2. The values of these components for all three designs are listed in Table 1, and were chosen based on the results from the equations above.Table 1: Capacitor and inductor selections at 35

11、0kHz, 700kHz, and 1600 kHz.Note that the DC resistance of each inductor decreased as the frequency increased. This is due to less copper length needed for fewer turns. The error amplifier compensation components were designed independently for each switching frequency. The calculations for selecting

12、 the compensation values are beyond the scope of this article.Minimum on-timeDigital converters-to-digital converter integrated circuits (IC) are characterized with a limit on the minimum controllable on-time, which is the narrowest achievable pulse width of the pulse width modulation (PWM) circuit.

13、 In a buck converter, the percentage of time that the field effect transistor (FET) is on during a switching cycle is called the duty cycle, and is equal tothe ratio of the output voltage to input voltage.For the converter example above, the duty cycle is 0.36 (1.8V/5.0V) and the minimum on-time of

14、the TPS54317 is 150ns (max) as shown in the datasheet. The limit for the controllable pulse width results in a minimum achievable duty cycle, which can be easily calculated as shown in Equation 3. Once the minimum duty cycle is known, the lowest achievable output voltage can be calculated, as shown

15、in Equation 4 and Table 2. The lowest output voltage is also limited by the reference voltage of the converter, which is 0.9V for the TPS54317.Equation 3:Minimum duty cycle =Minimum on-time x Switching frequencyEquation 4:Minimum V out =Vin x Minimum duty cycle (bounded by TPS54317 Vref)Table 2: Min

16、imum output voltage with 150 ns minimumon-time.In this example, a 1.8V output(a 1.2V output ) can be generated with a 1.6 MHz switching frequency. However, if the frequency is 3MHz, the lowest possible output voltage is limited to 2.3 V and the DC/DC converter will skip pulses. The alternative is to

17、 lower the input voltage or reduce the frequency. It is a good idea to check the DC/DC converter datasheet for a guaranteed minimum controllable on-time before selecting a switching frequency.Pulse SkippingPulse skipping occurs when the DC/DC converter cannot extinguish the gate drive pulses fast en

18、ough to maintain the desired duty cycle. The power supply will try to regulate the output voltage, but the ripple voltage will increase due to the pulses being further apart. Due to the pulse skipping, the output ripple will exhibit sub-harmonic components, which may present noise issues. It is also

19、 possible that the current limit circuit will no longer work properly since the IC may not respond to a large current spike. In some cases, the control loop may be unstable since the controller is not performing properly.The minimum controllable on-time is an important attribute andit is wise to che

20、ck the DC/DC converter's specification in thedatasheet to verify a frequency and minimum on-time combination.Efficiency and Power DissipationThe efficiency of a DC/DC converter is one of the most important attributes to consider when designing a power supply. Poor efficiency translates into high

21、er power dissipation which has to be managed on the circuit board with heat sinks or additional copper on the printed circuit board. Power dissipation also places a higher demand on the power supply upstream. Power dissipation has several components shown below: The loss components of interest from

22、our three examples come from the FET driving loss, the FET switching loss and the inductor loss. The FET resistance and IC loss are consistent since the same IC is used in all three designs. Since ceramic capacitors were chosen in each example, the capacitor loss is negligible due to their low equiv

23、alent series resistance. To show the effects of high frequency switching, the efficiency of each example was measured and illustrated in Figure 2.Figure 2: Efficiency at 5 V input and 1.8 V output at various frequencies.The figure clearly shows that the efficiency is decreased as switching frequency

24、 is increased. To improve efficiency at any frequency, look for a DC/DC converter with a low Rds (on), gate charge, or quiescent current specification at full load, or search for capacitors and inductors with lower equivalent resistance.SizeTable 3 shows the inductor and capacitor values with the pa

25、d area required on the printed circuit board.Table 3: Component size and total area requirementsThe recommended pad area of a capacitor or inductor is slightly larger than the individual component itself, and the pad area dimension is accounted for in each of the three design examples. Then, the tot

26、al area was derived by adding the area occupied by each component, which includes the pad sizes for the IC, the filter and all other small resistors and capacitors multiplied by a factor of two to account for component spacing. The total area savings from 350 kHz to 1600 kHz is significant and provi

27、des a 50 percent reduction in filter size and a 35 percent reduction in board space, saving almost 100mm2.However, the law of diminishing returns applies since the capacitance and inductance values cannot be reduced to nothing! In other words, pushing the frequency higher will not continually reduce

28、 the overall size since there is a limitation to appropriately sized mass produced inductors and capacitors.Transient ResponseThe transient response is a good indicator of the performance level of a power supply. A Bode plot of each power supply was taken to show a comparison at higher switching fre

29、quencies. As shown in Figure 3, the phase margin of each power supply is between 45 and 55 degrees, indicating a well-dampened transient response.Figure 3: Bode plots at 350 kHz, 700 kHz, and 1600 kHz.The cross over frequency is approximately one-eighth of the switching frequency. When using a fast

30、switching DC/DC converter, make sure the power IC error amplifier has enough bandwidth to support a high crossover frequency. The TPS54317 error amplifier unity gain bandwidth is typically 5MHz. The actual transient response times are shown in Table 4 with the associated voltage peak overshoot value

31、.Table 4: Transient response.The overshoot value is significantly lower with the higher switching frequency, due to the wider bandwidth. Lower transient voltage overshoots are desirable with newer performance processors as their regulation accuracy requirement may be three percent including transien

32、t voltage peaks.When higher output currents are needed, Texas Instruments offers the TPS40140 stackable, dual-channel, 1 MHz DC/DC controller using external MOSFETs. The benefits of a fast switching frequency can be realized by interleaving a number of power stages and switching them out of phase.Fo

33、r example, four outputs can be tied together switching at 500 kHz each, for an effective frequency of 2 MHz. The benefits are lower ripple, reduced input bulk capacitance, faster transient response, and better thermal management by spreading out the power dissipation over the circuit board. Up to ei

34、ght TPS40140 devices can be connected and synchronized out of phase via digital bus for a maximum effective frequency of 16 MHz.SummaryThere are tradeoffs to designing high-frequency switching converters. Some of the advantages shown in this article are a smaller size, faster transient response and

35、smaller voltage over and undershoots. On the other hand, the main penalty paid is a reduction of efficiency and increased heat dissipation.There are potential pitfalls to pushing the envelope such as pulse skipping and noise issues. When selecting a DC/DC converter for high frequency applications, c

36、heck the manufacturer' sdatasheet for important specifications such as the minimum on-time, the gain-bandwidth of the error amplifier, the FET resistance and switching loss. Integrated circuits that perform well in these specifications will cost a premium, but will beworth the price and much eas

37、ier to use when cornered with a tough design problem.选择 DC/DC 转换器最佳开关频率作者 : 德州仪器 Richard Nowakowski 及 Brian King提高开关频率的好处很明显，但也有些缺点，设计人员应了 解其中的得失利弊，才能选择最合适的开关频率来加以应 用。这篇实用文章将逐一说明这些考虑因素。开关频率很高的直流电源转换器 (DC/DC) 正逐渐流行， 因为 它们可以藉由较小的输出电容和电感，进而节省电路板面 积。但另一方面，负载点电源的需求量却随着处理器核心电 压降到 1V 以下而变得更严苛，这使得电源供应受到负载周

38、期减少的影响，很难在频率更高的情形下达到所要求的更低 电压。许多电源组件供货商正在大力推销速度更快的直流电源转 换器，并且宣称他们的产品可以节省空间。 一个以 1 或 2MHz 速率切换的直流电源转换器听起来很棒，但设计人员除了关 心体积与效率外，还应该了解其它会对电源供应系统带来冲 击的因素。本文将提供几个设计范例，说明提高开关频率的 各种优缺点。选择应用 为了说明高开关频率的得失利弊，本文设计和实作了三种不 同的电源供应，它们的输入电压都是5V，输出电压是1.8V ,而输出电流则为 3A，这些都是 DSP、ASIC 或FPGA等高 效能处理器常见的电源要求。在滤波器设计和效能的限制 下，这

39、些设计最多允许 20mV 涟波电压， 大约等于输出电压 的 1%，峰对峰的电感电流则设为 1A。本文中将会比较 350、 700 和 1600kHz 等不同频率的设计， 藉以说明它们的优缺点。这些范例都以德州仪器 (TI) 的 TPS54317 做为稳压器， 它是一款内建 MOSFET 的 1 .6MHz 、 低电压、 3A 同步直流降压转换器，具有可程序频率和外部 补偿电路，专用于高密度处理器电源负载点应用。 选择电感与电容 电感与电容都是依据下列简单的公式来选择： 公式 1 ：V = L 为i/dt整理后可得：L 三 Vout X (1-D) / ( I x Fs)其中 I = 1A 峰对

40、峰值；D = 1.8V/5V = 0.36。公式 2：I = CdXv/dt 整理后可得：2 x A I / (8 x Fs x V)其中：A V = 20 mV , I = 1A峰对峰值。方程式 2 假设电容的串联阻抗可忽略， 如陶瓷电容， 所以本 文中的三个设计都选择使用阻抗和体积都很小的陶瓷电容。 在重新整理后的公式 2 中，乘数 2 代表直流偏压造成的电 容值下降，这是因为多数陶瓷电容的资料表都未将此效应列 入考虑。本文利用图 1 中的电路评估三种设计分别的效能。图 1 ： TPS54317 参考电路图图 1 里有些组件未标示数值， 那是因为这些组件在三种设计 里的数值都不相同。输出滤

41、波器由 L1 和 C2 组成，它们在 三种设计里的数值分别如表 1 所列，这些数值都是根据前面 的公式计算而得。表 1：频率为 350kHz、700kHz 和 1600kHz 时所选择的电容 值和电感值注意频率越高，电感所需的圈数就越少，所以直流阻抗就越 低。这些误差放大器的补偿零件都是针对本文中的三种开关 频率所设计，但这里不会讨论如何计算及选择这些组件值。 最小导通时间数字化直流电源转换器所能控制的最小导通时间，是由脉冲 宽度调变 （PWM） 电路所能产生的最小脉冲宽度决定。在降 压转换器里， FET 导通时间在整个开关周期所占的比例称为 负载周期 （duty cycle） ，它等于输出电

42、压与输入电压的比值。 例如在图 1 电路里， TPS54317 的负载周期从数据表可发现 为 0.36 （1.8V/5.0V） ，最小导通时间则为 150ns （最大值 ） 。设 计人员只要根据组件所能控制的最小脉冲宽度，就能利用公 式 3 轻易算出电路所能达到的最小负载周期，再利用公式 4 计算转换器所能提供的最低输出电压（参考表 2）。值得注意的是，转换器的最低输出电压也会受到参考电压的限制，例如 TPS54317 的参考电压就是 0.9V 。公式 3最小负载周期=最小导通时间x 开关频率（3）公式 4最小输出电压=输入电压x 最小负载周期（不得低于 TPS54317 的参考电压 ） （4

43、）表 2：最小导通时间为 150ns 时的最小输出电压在此例中， 1.6MHz 开关频率的最小输出电压限制为 1.2V（译注：原文此处误为 1.8V） 。但若频率升至 3MHz ，最小输 出电压限制就会增到 2.3V 。如果直流电源转换器要提供更低 的输出电压，就必须省略部份脉冲、降低输入电压或减少开 关频率。设计人员在选择直流电源转换器的开关频率前，最 好先查询数据表，确保组件所能控制的最小导通时间符合设 计要求。省略脉冲 若转换器停止闸极驱动脉冲的速度不够快，无法达到所要求 的负载周期， 转换器便会省略部份脉冲 (Pulse Skipping) 以提 供所需的低输出电压。此时，尽管电源供应

44、仍会努力保持输 出电压稳定，但涟波电压仍会因为脉冲间隔变大而升高。由 于省略脉冲的关系，输出涟波会出现某些次谐波成份，这可 能会带来噪声的问题。限流电路也可能无法正常操作，因为 组件或许不会对大电流突波做出响应。有时甚至控制器都不 能正常工作，致使控制回路变得不稳定。最快可控制导通时 间是直流电源转换器的一项重要参数，设计人员应检查组件 数据表所列的规格，确保开关频率和最小导通时间都符合要 求。效率与功耗 直流电源转换器的效率是电源供应设计最重要的考虑因素 之一。低效率等于高耗电，需要在电路板上安装散热片或扩 大铜箔面积才能排除热量。另外，高耗电也会对上游电源造 成很大的负担。功耗来源有下列几种：影响因素功耗来源闸极电荷、驱动电压和频率的函数 FET驱动功耗输入电压、输出电流、 FET FET 开关功耗 升起 /下降时间 以及频率的函数12 X导通阻抗 FET阻抗12 X直流阻抗+交流核心功耗 电感功耗IRMS2 电容功耗 X 等效串联组抗 查询数据表，找出组件操作时的 Iq 组件功耗 (Iq) 在这三个例子里， 主要功耗来源包括 FET 驱动功耗、 FET 开 关功耗和电感功耗。 FET 阻抗与组件功耗则没有区别， 因为 这三个设计使用同一个组件。电容功耗也可以忽略，因为它 们都使用等效串联阻抗很小的陶瓷电容。为了展示高频开关 的影响，图 2 绘出了这些