北邮数字电路与逻辑设计实验

1、 北京邮电大学数字电路与逻辑设计实验 学院：电子工程学院 班级： 姓名： 学号： 班内序号： 实验一 Quartus II原理图输入法设计1、 实验目的：(1)熟悉Quartus II原理图输入法进行电路设计和仿真。(2)掌握Quartus II 图形模块单元的生成与调(3)熟悉实验板的使用二、实验所用器材：(1)计算机(2)直流稳压电源(3)数字系统与逻辑设计实验开发板三、实验任务要求(1)用逻辑门设计实现一个半加器，仿真验证其功能，并生成新的半加器图形模块单元。(2)用(1)中生成的半加器模块和逻辑门设计实现一个全加器，仿真验证其功能，并下载到实验板测试，要求用拨码开关设定输入信号，发光二

2、极管显示输出信号。(3)用VHDL语言实现全加器。四、VHDL代码和实验波形图1、 全加器VHDL代码：library ieee;use ieee.std_logic_1164.all;entity bjq isport(a,b:in std_logic;co,so:out std_logic);end entity bjq;architecture a of bjq isbeginso<= a xor b;co<= a&#

3、160;and b;end;library ieee;use ieee.std_logic_1164.all;entity qjq isport(ain,bin,cin:in std_logic;cout,sum:out std_logic);end entity qjq;architecture a of qjq iscomponent bjqport(a,b:in std_logic;co,so:out std_logic);end

4、 component;signal d,e,f:std_logic;beginu1:bjq port map(a=>ain,b=>bin,co=>d,so=>e);u2:bjq port map(a=>e,b=>cin,co=>f,so=>sum);cout<=d or f;end;2、 原理图半加器：全加器：3、全加器波形图波形分析：其中ain，bin为全加器输入，cin为低位的进位，cout为进位输出，sum为和。由图可看出，波形仿真了输入由000-111的

5、情况，每种情况竖着看为真值表，易得出其确实完成了全加器功能。实验三 VHDL组合逻辑电路设计一、实验目的：(1)熟悉Quartus II原理图输入法进行电路设计和仿真。(2)掌握Quartus II 图形模块单元的生成与调(3)熟悉实验板的使用二、实验所用器材：(1)计算机(2)直流稳压电源(3)数字系统与逻辑设计实验开发板三、实验任务要求用VHDL语言设计将8421计数器，分频器和数码管译码器连接使用，实现在指定数码管滚动显示0-9，其余数码管不亮，并带有清零功能，并下载到实验板显示计数结果。四、 VHDL代码和实验波形图1. VHDL代码library ieee;use ieee.std_

6、logic_1164.all;use ieee.std_logic_unsigned.all;entity fen isport( clk,clr:in std_logic; b:out std_logic_vector(6 downto 0); c:out std_logic_vector(5 downto 0); end fen; architecture ar of fen is signal tmp:integer range 0 to 12500000; signal out1:std_logic; signal qtemp:std_logic_vector(3 downto 0);

7、 begin p1:process(clk,clr) begin if clr=0 then tmp<=0; elsif clk'event and clk='1' then if tmp=12499999 then tmp<=0;out1<=not out1;else tmp<=tmp+1;end if;end if;end process; p2:process(out1,clr)begin if clr='0' then qtemp<="0000" elsif(out1'event and

8、out1='1')thenif qtemp="1010"then qtemp<="0000"else qtemp<=qtemp+1;end if;end if;end process;p3:process(qtemp) begin case qtemp is when"0000" => b<="1111110" when"0001" => b<="0110000" when"0010" => b&l

9、t;="1101101" when"0011" => b<="1111001" when"0100" => b<="0110011" when"0101" => b<="1011011" when"0110" => b<="1011111" when"0111" => b<="1110000" when"10

10、00" => b<="1111111" when"1001" => b<="1111011" when others => b<="0000000" end case; c<="111011" end process; end; 2.连接图输入为clk和clr，clk为需要分频时钟，clr为异步清零端，输出为b和c，b连接7段数码管，c决定是哪一个亮。3.引脚图：4仿真波形（仿真使用的10分频）：波形分析：由波形可看出分频器完成了10分频，并且

11、计数器也按分频后时钟计数，并输出至译码端b，可以看书数码管显示值与计数值相符，c也与预设相同，clr也完成了异步清零，完成了整体功能。实验四 VHDL组合逻辑电路设计一、实验目的：(1)熟悉Quartus II原理图输入法进行电路设计和仿真。(2)掌握Quartus II 图形模块单元的生成与调(3)熟悉实验板的使用二、实验所用器材：(1)计算机(2)直流稳压电源(3)数字系统与逻辑设计实验开发板三、实验任务要求（1）用 VHDL 语言设计并实现一个 8×8 点阵行扫描控制器，要求从上至下逐行循环 点亮点阵（红色或绿色均可），每行点亮时间为 0.5 秒。 （2）用 VHDL 语言设计

12、并实现一个 8×8 点阵行扫描控制器，要求从上至下逐行点亮 点阵，第一行为红色，第二行为绿色，依次类推，直至点亮所有行，然后全部熄灭，再重新从第一行开始。四、VHDL代码和实验波形图1. VHDL代码（1）点阵扫描library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity kdwdz1 isport(clk,clear:in std_logic; colr:out std_logic_vector(7 downto 0); row:out std_logic_vector(7 down

13、to 0);end kdwdz1;architecture a of kdwdz1 issignal temp: integer range 0 to 4;signal clk_temp:std_logic;signal q:std_logic_vector(2 downto 0);beginp1:process(clear,clk) begin if clear='0' then temp <= 0; elsif (clk'event and clk ='1')then if temp = 4 then temp<=0;clk_temp &

14、lt;= not clk_temp; else temp<=temp+1; end if; end if; end process p1;p2:process(clear,clk_temp) begin if clear='0' then q<="000" elsif (clk_temp'event and clk_temp = '1') then q <=q+1; else q<=q; end if; end process p2;p3:process(q) begin case q is when &quo

15、t;000"=>colr<="11111111" row<="11111110" when "001"=>colr<="11111111" row<="11111101" when "010"=>colr<="11111111" row<="11111011" when "011"=>colr<="11111111" ro

16、w<="11110111" when "100"=>colr<="11111111" row<="11101111" when "101"=>colr<="11111111" row<="11011111" when "110"=>colr<="11111111" row<="10111111" when "111"=

17、>colr<="11111111" row<="01111111" when others =>colr<="00000000" row<="11111111" end case; end process p3;end; （2）逐行亮library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity kdwdz2 isport(clk,clear:in std_logic; colr:ou

18、t std_logic_vector(7 downto 0); colg:out std_logic_vector(7 downto 0); row:out std_logic_vector(7 downto 0);end kdwdz2;architecture a of kdwdz2 issignal temp: integer range 0 to 12499999;signal temp1: integer range 0 to 49999;signal clk_temp:std_logic;signal clk_temp1:std_logic;signal q:std_logic_ve

19、ctor(2 downto 0);signal b:std_logic_vector(2 downto 0);beginp1:process(clear,clk) - fruquncy divide begin if clear='0' then temp <= 0; elsif (clk'event and clk ='1')then if temp = 12499999 then temp<=0;clk_temp <= not clk_temp; else temp<=temp+1; end if; end if; end p

20、rocess p1;p11:process(clear,clk) - fruquncy divide begin if clear='0' then temp1 <= 0; elsif (clk'event and clk ='1')then if temp = 49999 then temp1<=0;clk_temp1 <= not clk_temp1; else temp1<=temp1+1; end if; end if; end process p11;p2:process(clear,clk_temp) -counter

21、 begin if clear='0' then q<="000" elsif (clk_temp'event and clk_temp = '1') then q <=q+1; else q<=q; end if; end process p2;p21:process(clear,clk_temp1) -counter begin if clear='0' then b<="000" elsif (clk_temp1'event and clk_temp1= 

22、9;1') then b <=b+1; else b<=b; end if; end process p21;p3:process(q,b) -light red or green begin case q is when "000"=>colr<="11111111" colg<="00000000" row<="11111110" when "001"=> case b is when "000"=>colr<

23、="11111111" colg<="00000000" row<="11111110" when "001"=>colr<="00000000" colg<="11111111" row<="11111101" when others =>colr<="00000000" colg<="00000000" row<="11111111"

24、 end case; when "010"=>case b is when "000"=>colr<="11111111" colg<="00000000" row<="11111110" when "001"=>colr<="00000000" colg<="11111111" row<="11111101" when "010"=>c

25、olr<="11111111" colg<="00000000" row<="11111011" when others =>colr<="00000000" colg<="00000000" row<="11111111" end case; when "011"=>case b is when "000"=>colr<="11111111" colg&l

26、t;="00000000" row<="11111110" when "001"=>colr<="00000000" colg<="11111111" row<="11111101" when "010"=>colr<="11111111" colg<="00000000" row<="11111011" when "011"

27、;=>colr<="00000000" colg<="11111111" row<="11110111" when others =>colr<="00000000" colg<="00000000" row<="11111111" end case; when "100"=>case b is when "000"=>colr<="11111111"

28、 colg<="00000000" row<="11111110" when "001"=>colr<="00000000" colg<="11111111" row<="11111101" when "010"=>colr<="11111111" colg<="00000000" row<="11111011" when "0

29、11"=>colr<="00000000" colg<="11111111" row<="11110111" when "100"=>colr<="11111111" colg<="00000000" row<="11101111" when others =>colr<="00000000" colg<="00000000" row<

30、="11111111" end case; when "101"=>case b is when "000"=>colr<="11111111" colg<="00000000" row<="11111110" when "001"=>colr<="00000000" colg<="11111111" row<="11111101" when

31、"010"=>colr<="11111111" colg<="00000000" row<="11111011" when "011"=>colr<="00000000" colg<="11111111" row<="11110111" when "100"=>colr<="11111111" colg<="0000000

32、0" row<="11101111" when "101"=> colr<="00000000" colg<="11111111" row<="11011111" when others =>colr<="00000000" colg<="00000000" row<="11111111" end case; when "110"=>case b

33、is when "000"=>colr<="11111111" colg<="00000000" row<="11111110" when "001"=>colr<="00000000" colg<="11111111" row<="11111101" when "010"=>colr<="11111111" colg<="

34、;00000000" row<="11111011" when "011"=>colr<="00000000" colg<="11111111" row<="11110111" when "100"=>colr<="11111111" colg<="00000000" row<="11101111" when "101"=> c

35、olr<="00000000" colg<="11111111" row<="11011111" when "110"=> colr<="11111111" colg<="00000000" row<="10111111" when others =>colr<="00000000" colg<="00000000" row<="111111

36、11" end case; when "111"=>case b is when "000"=>colr<="11111111" colg<="00000000" row<="11111110" when "001"=>colr<="00000000" colg<="11111111" row<="11111101" when "010&quo

37、t;=>colr<="11111111" colg<="00000000" row<="11111011" when "011"=>colr<="00000000" colg<="11111111" row<="11110111" when "100"=>colr<="11111111" colg<="00000000" row<="11101111" when "101"=> colr<="00000000" colg<="11111111&q