毕业设计论文外文资料翻译〔含原文〕

1、南京理工大学毕业设计（论文）外文资料翻译教 学 点：南京信息职业技术学院专 业：电子信息工程姓名：暨适学号： 014910253034外文由处： Pci System Architecture （用外文写）附 件：1.外文资料翻译译文；2.外文原文。指导教师评语：该生外文翻译没有基本的语法错误，用词准确，没 有重要误译，忠实原文；译文通顺，条理清楚，数量与 质量上达到了本科水平。签名：年 月 日注：请将该封面与附件装订成册1 ：外文资料翻译译文64 位 PCI 扩展1. 64 位数据传送和64 位寻址：独立的能力PCI 规范给出了允许64 位总线主设备与64位目标实现64位数据传送的机理。在传

2、送的开始，如果回应目标是一个64 位或 32 位设备， 64 位总线设备会自动识别。如果它是 64 位设备，达到8 个字节 （一个 4 字） 可以在每个数据段中传送。假定是一串0 等待状态数据段。在33MHz 总线速率上可以每秒264兆字节获取（8 字节传送33 百万传送字秒），在 66MHz 总线上可以528M 字节秒获取。如果回应目标是32位设备，总线主设备会自动识别并且在下部 4位数据通道上（AD31:00）引导，所以数据指向 或来自目标。规范也定义了64 位存储器寻址功能。此功能只用于寻址驻留在4GB 地址边界以上的存储器目标。32 位和64 位总线主设备都可以实现64 位寻址。此外，

3、对64 位寻址反映的存储器目标（驻留在4GB 地址边界上）可以看作32 位或 64 位目标来实现。注意 64 位寻址和64 位数据传送功能是两种特性，各自独立并且严格区分开来是非常重要的。一个设备可以支持一种、另一种、都支持或都不支持。2. 64 位扩展信号为了支持64位数据传送功能，PCI 总线另有39个引脚。REQ64# 64位总线主设备有效表明它想执行64位数据传送操作。REQ64%FRAME#号具有相同的时序和间隔。REQ64信号必须由系统主板上的上拉电阻来支持。 当32位总线主设备进行传送时,REQ64#能又漂移。ACK64#m标有效以回应被主设备有效的REQ64#如果目标支持64位

4、数据传送），ACK64#! DEVSEL#有相同的时序和间隔（但是直到REQ64#主设备有效，ACK64# 才可被有效）。像REQ64#样，ACK64得号线也必须由系统主板上的上拉电阻来支持。 当32位设备是传送目标时，ACK64痂能漂移。AD64:32 包含上部4位地址数据通道。C/BE#7:4 包含高 4位命令/字节使能信号。PAR6较为上部4个AD1道和上部4位C/BE信号线提供偶校验的奇偶校验位。以下是几小结详细讨论64 位数据传送和寻址功能。3. 在 32 位插入式连接器上的64 位卡安装在 32 位扩展槽上的64 位卡只能自动地使用总线的下半部来执行传送，这是事实，因为系统主板的设

5、计者将连接器上的 REQ64输出弓唧和ACK64榆入引脚与系统主板 上的上拉电阻分别连接而没有其它连接。当64位总线主设备安装在32位插槽并开始交易时，对于任何目标REQ64的有效是 不可见的。此外，ACK64编出总被采样无效（因为它在系统主板上被上拉）,这就迫使总 线主设备在传送时只能使能总线下部分。而且， 如果交易中被寻址的目标是64 位的， 它会采样无效的REQ64#因为它在系统主板上被上拉），这就迫使目标在传送时只能利用 总线下部分，并且使ACK64榆出为不可用。在自身卡上的64位扩展信号线在它们使用时不能有漂移。如果插卡上的 COMSJ入 接收器出现振动和泄露过量的电流，这就违反了规

6、范的“绿色”原则。当插卡安装在 32 位槽时，它不能使用总线的上半部。插卡检测插槽的类型的方法（在启动开始时采样REQ64#效）下一节将描述。4. 当未使用时，上拉可防止64位扩展的漂移在未使用时如果允许 64位扩展信号（AD63:32、C/BE7:4和PAR64漂移，那 么插卡上的CMO输入缓存器将振动并且泄漏过量电流。当不再使用时 ，为了防止扩展的 漂移，要求系统主板设计者在扩展信号上加上拉电阻来防止漂移，因为这些上拉电阻可保证扩展位不漂移，嵌入在系统板上的64 位设备和安装在64 位 PCI 插入式连接器上的64 位卡，当它们不使用扩展位位时，不需要采取任何特殊措施防止扩展槽漂移。64

7、位扩展在以下环境中不使用：1. PCI 总线空闲。2. 32 位总线组设备正与一个32 为目标进行交易。3. 32位总线主设备与一个64位目标进行交易，当在交易的起始检测到REQ64#效 时，目标不用总线的上半部。4. 64位总线主设备寻址一个目标已进行 32位数据传送（REQ64#效）,并且目标 驻留在低于4GB地址边界以下（在地址段和数据段不使用总线上半部）。不管目标是32 位还是64位，在数据中不使用总线的上半部（因为 REQ64#效）。5. 一个64位总线主设备试图与驻留在4GBi界以下的32位存储器目标进行传送时 （REQ64#效）。在此情况下，主设备在地址段中只能使用总线的下半部分

8、 （因为它仅生 成32位地址）。当它发现当前寻址的目标是 32位目标时（当DEVSEL#效时ACK64痂能 有效） ，主设备在数据段中停止使用总线的下半部。4.1 32位 PCI 连接器上的64位插卡64 位卡允许安装在32 位卡插卡连接器上。连接器的主要部分（32 位）包括所有32位 PCI 信号， 同时连接器的扩展包含64位信号 （除了放置在连接器32位部分的REQ64#和 ACK64#） .当64位设备安装在 32位扩展槽上时，在AD63:32、C/BE7:4和PAR64k的系统主板上拉对插入式卡是不可用的。这就意味着连接到扩展信号号上的插入式输入缓存 器将会漂移，震动和泄漏电流。规范中

9、强调插入卡设计者不能通过在插入卡的扩展线上提供上拉电阻来解决这个问题， 当卡安装在64 位扩展槽中用此方法会引起一些问题，在这些信号线上会需要2 套上拉电阻 （一套在插卡上，另一套在系统主板上）。 如果所有设计者都用此方法，若共有多个 64 位插卡的设备装入连接器上时，将会由多个上拉电阻在扩展信号线上，这就会造成上拉电阻过载。规范中对一个64 位插卡给出了如何在起始时间确定是安装在了32 位连接器上还是64 位连接器上的方法。如果插卡检测出被插入了64 位连接器上时，系统主板上的上拉电阻可在扩展信号不使用时防止卡上的输入接受不漂移；另一方面，如果 64 位插卡检测出被插入32 位卡连接器上时，

10、卡上的逻辑可防止输入接收器的漂移，规范中列举了近似于以下几种方法：将输入缓存器关闭。不断的驱动输出（因为它们没有连接任何器件）。4.2 64 位插卡如何确定所安装插槽的类型当系统被加电时，复位信号会自动被有效。在此期间，系统主板上的逻辑必须有效REQ64#还有RST# REQ64#面有一个上拉电阻与集成在系统主板上的所有64位设备和所有64位PCI扩展槽上的REQ64#|脚相连。规范指出了每个 32位PCI扩展槽上的 REQ64信号线（REQ64# ACK64散置在连接器的32位部分）,每一个都有自己独立的上 拉电阻。在复位期间，系统主板复位逻辑最初有效 PCI RST#W号同时供电电源的PO

11、WERGOOD 信号被无效。在RST#T效过程中，系统主板逻辑有效 REQ64#保持有效直至它消除了 RST醋号。在POWERGOOD源逻辑有效时，系统主板复位逻辑会无效PCI RST蛤号。在RST#T效的尾部边7ft,要求所有64位设备采样REQ64信号的状态。嵌入在系统主板或安装在 64位扩展槽上的所有64位设备在RST#勺尾沿采样REQ#有效，这就要求它们镰刀系统主板上的扩展上拉电阻上并且当不使用它们时不需要采取特殊措施防止扩展信号漂移。安装在32位插卡槽上的所有 64位设备，在 RST#勺尾部边沿都可检测到无效的 REQ64#这就告知它们需要连接扩展信号上的系统主板的上拉电阻，插卡逻辑

12、必须对本 身的 64 位卡上的扩展信号线的状态负责。所以插卡必须使用前一节提过的方法之一，防止卡的输入接受器泄漏过量电流。2 ：外文原文The 64-bit PCI ExtensionThe 64-bit PCI ExtensionThis chapter describes the 64-bit extension that permits masters and targets to perform eight byte transfers during each data phase. It also describes 64-bit addressing used to address

13、 memory targets that reside above the 4GB boundary.1 64-bit Ata Transfers and 64-bit Addressing: Seperate CapabilitiesThe PCI specification provides a mechanism that permits a 64-bit bus master to perform 64-bit data transfers with a 64-bit target. At the beginning of a transaction, the 64-bit bus m

14、aser automatically senses if the responding target is a 64-bit or a 32-bit device. If sit a 64-bit device, up to eight bytes(a quadword) may be transferred during each data phase. Assuming a series of 0-wait state data phases, throughput of 264Mbytes/second can be achieved at a bus speed of 33MHz(8

15、bytes/transfer x 33 million transfers/second) and 528Mbytes/second at66MHz.If the responding target is a 32-bit device, the bus master automatically senses this and steers all data to or from the target over the lower four data paths(AD31:0).The specification also defines 64-bit memory addressing ca

16、pability. This capability is only used to address memory targets that reside above the 4GB address boundary. Both 32-and 64bit bus masters can perform 64-bit addressing. In addition, memory target(that reside over the 4GB address boundary) that respond to 64-bit addressing can be implemented as eith

17、er 32-or 64-bit targets.2 64-Bit Extension SignalsIn order to support the 64-bit data transfer capability, the PCI bus implements an additional thirty-nine pins:REQ64# is asserted by a 64-bit bus master to indicate that is would like to perform 64-bit data transfers.REQ64# has the same timing and du

18、ration a s the FRAME# signal. The REQ64# signal line must be supplied with a pull up resistor on the system board.REQ64# cannot be permitted to float when a 32-bit bus master is performing a transaction.ACK64# is asserted by a target in response to REQ64# assertion by the master (if the target suppo

19、rts 64-bit data transfers).ACK64# has the same timing and duration as DEVSEL#(but ACK64# must not be asserted unless REQ64# is asserted by the initiator).Like REQ64#,the AcK64# signal line must also be supplied with a pullup resistor on the system board.ACK64# cannot be permitted to float when a 32-

20、bit device si the target of transaction.AD 63:32 comprise the upper four address/data paths.C/BE# 7:4 comprise the upper four command/byte enable signals.PAR64 is the parity bit that provides even parity for the upper four AD paths and the upper four C/BE signal lines.The following sections provide

21、a detailed discussion of 64-bit data master and addressing capability.3 64-bit Cards in 32-bit Add-in ConnectorsA 64-bit card installed in a 32-bit expansion slot automatically only uses the lower half of the bus to perform transfers. This is true because the system board designer connects theREQ64#

22、 output pin and the ACK64# input pin on the connector to individual pull-ups on the system board and to nothing else.When a 64-bit bus master is installed in a 32-bit card slot and it initiates a transaction, its assertion of REQ64# is not visible to any of the target. In addition, its ACK64# input

23、is always sampled deasserted (because ist pulled up on the system board).This forces the bus master to use only the lower part of the bus during the transfer. Furthermore, if the target addressed in the transaction is a 64-bit target, it samples REQ74# deasserted (because sit pulled up on the system

24、 board),forcing it to only utilize the lower half of the bus during the transaction and to disable its ACK64# output.The 64-bit extension signal lines on the card itself cannot be permitted to float when they are not in use. The CMOS input receives on the card would oscillate and draw excessive curr

25、ent, thus violating the “green” aspect of the specification. hen the card is installed in a 32- bit slot, it cannot use the upper half of the bus. The manner in which the card detects the type of slot (REQ64# sampled deasserted at startup time) is described in the next section.4 Pullups Prevent 64-b

26、it Extension from Floating When Not in UseIf the 64-bit extension signals (AD63:32,C/BE7:4# and PAR64 are permitted to float when not in use, the CMOS input buffers on the card will oscillate and draw excessive current. In order to prevent the extension signals to keep them from floating. Because th

27、ese pull-ups are guaranteedto keep the extension from floating when not in use, 64-bit devices that are embedded on the system board and 64-bit cards installed in 64-bit PCI add-in connectors dotn need to take any special action to keep the extension from floating when they are not using it.The 64-b

28、it extension is not in use under the following circumstance: 1. The PCI bus is idle.2. A 32-bit bus master is performing a transaction with a 32-bit target.3. A 32-bit bus master is performing a transaction with a 64-bit target. Upon detecting REQ64# deassertedat the start of the transaction, the ta

29、rget will not use the upper half of the bus.4. A 64-bit bus master addresses a target to perform 32-bit data transfers (REQ64# deasserted)and the target resides below the 4GB boundary. In this case, the initiator only uses the lower half of the bus during the address phase(because it s only generati

30、ng a 32-bit address).When it discovers the currently-addressed target is a 32-bit target(ACK64# not asserted when DEVSEL# asserted),the initiator ceases to use the upper half at the bus during the data phases.4.1. a 64-bit Card in a 32-bit PCI ConnectorInstallation of a 64-bit card in a 32-bit card

31、connector is permitted. The main(32-bit) portion of the connector contains all of the 32-bit PCI signals, which an extension to the connector contains the 64-bit extension signal(with the exception of REQ64# and ACK64# which are located on the 32-bit portion of the connector).When a 64-bit device is

32、 installed in a 32-bit PCI expansion slot, the system board pull-ups on AD63:32,C/BE#7:4 and PAR64 are not available to the add-in card. This means that the add-in card s input buffers that are connected to the extension signal pins will float, oscillate, and draw excessive current.The specification

33、 states that the add-in card designer must not solve the problem by supplying pullup resistors on the extension lines on the add-in card. Using this approach would cause problems when the card is installed in a 64-bit expansion slot. There would then be tow sets of pullup resistor on these signal li

34、ne (the ones on the card plus the ones on the system board).If all designer solved the problem in this manner, a machine with multiple 64-bit cards inserted in 64-bit card connectors would have multiple pull-ups on the extension signal, resulting in pullup current overload.The specification provides

35、 a method for a 64-b9it card to determine at startup time whether its installed in a 32-bit or a 64-bit connector. If the card detects that it is plugged into a 64-bit connector, the pull-ups on the system board will keep the input receives on the card from floating when the extension is not in use.

36、 On the other hand, if a y64-bit card detects that it is a 32-bit card connector, the logic on the card must keep the input receives from switching. The specification states that an approach similar to one of the following should be use: Biasing the input buffer to turning it off.Actively driving th

37、e outputs continually (since they aren t connected to anything).4.2. How 64-bit Card Determines Type of Slot installed InWhen the system is powered up, the reset signal is automatically asserted.During this period of time, the logic on the system board must assert the REQ64# signal as well as RST#.R

38、EQ64# has a single pullup resistor on it and is connected to the REQ64# pin on all 64-bit devices integrated onto the system board and on all 64-bit PCI expansion slot. The specification states that the REQ64# signal line on each 32-bit PCI expansion slot (REQ64# and ACK64# are located on the 32-bit portion of the connector), however, each has