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1、实用标准文案十五计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_ve ctor(3 downto 0);END fiveteencout;ARCHITECTURE counter OF fiveteencout IS SIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(cl
2、k,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1110") THEN count_int<="0000"ELSEcount_int <= count_int 1;文档大全实用标准文案-ELSE- -NULL ;- -IF (count_int="1001") T
3、HEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- -IF (reset='0') then-q<="0000"- -ELSIF(clk'event and clk='1') THEN- -q<=q 1;- -IF (q<="1001") then-q<="0000"- -END IF;- -IF (reset<='1')THEN-q&
4、lt;="00"-ELSIF- -wait until (clk'event and clk='1');- -WAIT UNTIL (clk'EVENT AND clk = '1');- -WAIT UNTIL (clock'EVENT AND clock = '1');- -q<=q '1'文档大全实用标准文案-end if;-count<=q;- -WAIT UNTIL clock = '1'- -if (clock'event and clock
5、='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'clock = '1');clock = '1');-count <= 0;-WAIT UNTIL (clock'EVENT AND-WAIT riseedge clock = '1'-if (clock'event and clock='1') then- -WAIT UNTIL rising_edge(clock);- -count &
6、lt;= 1;- -WAIT UNTIL (clock'EVENT AND- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then- -WAIT UNTIL rising_edge(clock);-count <= 2;-end if;- -end if;- -end if;- -END PROCESS;END counter;文档大全实用标准文案十四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic
7、_unsigned.all;ENTITY fourteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_ve ctor(3 downto 0);END fourteencout;ARCHITECTURE counter OF fourteencout IS SIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENco
8、unt_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1101") THEN count_int<="0000"ELSEcount_int <= count_int 1;文档大全实用标准文案-ELSE- -NULL ;- -IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <
9、= count_int;- -IF (reset='0') then-q<="0000"- -ELSIF(clk'event and clk='1') THEN- -q<=q 1;- -IF (q<="1001") then-q<="0000"- -END IF;- -IF (reset<='1')THEN-q<="00"-ELSIF- -wait until (clk'event and clk='1
10、9;);- -WAIT UNTIL (clk'EVENT AND clk = '1');- -WAIT UNTIL (clock'EVENT AND clock = '1');- -q<=q '1'文档大全实用标准文案-end if;-count<=q;- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and c
11、lock='1'clock = '1');clock = '1');-count <= 0;-WAIT UNTIL (clock'EVENT AND-WAIT riseedge clock = '1'-if (clock'event and clock='1') then- -WAIT UNTIL rising_edge(clock);- -count <= 1;- -WAIT UNTIL (clock'EVENT AND- -WAIT UNTIL clock = '1&
12、#39;- -if (clock'event and clock='1')then- -WAIT UNTIL rising_edge(clock);-count <= 2;-end if;- -end if;- -end if;- -END PROCESS;END counter;文档大全实用标准文案十三计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY thireteencout ISPORT(clk,reset,enable : IN std_lo
13、gic; count : OUT std_logic_ve ctor(3 downto 0);END thireteencout;ARCHITECTURE counter OF thireteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1'
14、THENIF(count_int="1100") THENcount_int<="0000"ELSEcount_int <= count_int 1;文档大全实用标准文案-ELSE- -NULL ;- -IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- -IF (reset='0') then-q<="0000"- -E
15、LSIF(clk'event and clk='1') THEN- -q<=q 1;- -IF (q<="1001") then-q<="0000"- -END IF;- -IF (reset<='1')THEN-q<="00"-ELSIF- -wait until (clk'event and clk='1');- -WAIT UNTIL (clk'EVENT AND clk = '1');- -WAIT UNTIL
16、 (clock'EVENT AND clock = '1');- -q<=q '1'文档大全实用标准文案-end if;-count<=q;- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'clock = '1');clock = '1');-count <
17、= 0;-WAIT UNTIL (clock'EVENT AND-WAIT riseedge clock = '1'-if (clock'event and clock='1') then- -WAIT UNTIL rising_edge(clock);- -count <= 1;- -WAIT UNTIL (clock'EVENT AND- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then- -WAIT UNTIL ri
18、sing_edge(clock);-count <= 2;-end if;- -end if;- -end if;- -END PROCESS;END counter;文档大全实用标准文案十二计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY twelvecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_ve ctor(3 downto 0);END twelvecout;ARCHITECTU
19、RE counter OF twelvecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1011") THENcount_int<="0000"ELSEcount
20、_int <= count_int 1;文档大全实用标准文案-ELSE- -NULL ;- -IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- -IF (reset='0') then-q<="0000"- -ELSIF(clk'event and clk='1') THEN- -q<=q 1;- -IF (q<="10
21、01") then-q<="0000"- -END IF;- -IF (reset<='1')THEN-q<="00"-ELSIF- -wait until (clk'event and clk='1');- -WAIT UNTIL (clk'EVENT AND clk = '1');- -WAIT UNTIL (clock'EVENT AND clock = '1');- -q<=q '1'文档大全实用标准文案-en
22、d if;-count<=q;- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'clock = '1');clock = '1');-count <= 0;-WAIT UNTIL (clock'EVENT AND-WAIT riseedge clock = '1'-if (clo
23、ck'event and clock='1') then- -WAIT UNTIL rising_edge(clock);- -count <= 1;- -WAIT UNTIL (clock'EVENT AND- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then- -WAIT UNTIL rising_edge(clock);-count <= 2;-end if;- -end if;- -end if;- -END PROCESS;END
24、 counter;文档大全实用标准文案十一计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY elevencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_ve ctor(3 downto 0);END elevencout;ARCHITECTURE counter OF elevencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROC
25、ESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1010") THENcount_int<="0000"ELSEcount_int <= count_int 1;文档大全实用标准文案-ELSE- -NULL ;- -IF (count_int="1001&quo
26、t;) THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- -IF (reset='0') then-q<="0000"- -ELSIF(clk'event and clk='1') THEN- -q<=q 1;- -IF (q<="1001") then-q<="0000"- -END IF;- -IF (reset<='1')TH
27、EN-q<="00"-ELSIF- -wait until (clk'event and clk='1');- -WAIT UNTIL (clk'EVENT AND clk = '1');- -WAIT UNTIL (clock'EVENT AND clock = '1');- -q<=q '1'文档大全实用标准文案-end if;-count<=q;- -WAIT UNTIL clock = '1'- -if (clock'event and
28、clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'clock = '1');clock = '1');-count <= 0;-WAIT UNTIL (clock'EVENT AND-WAIT riseedge clock = '1'-if (clock'event and clock='1') then- -WAIT UNTIL rising_edge(clock);- -co
29、unt <= 1;- -WAIT UNTIL (clock'EVENT AND- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then- -WAIT UNTIL rising_edge(clock);-count <= 2;-end if;- -end if;- -end if;- -END PROCESS;END counter;文档大全实用标准文案十计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_l
30、ogic_unsigned.all;ENTITY count ISPORT(clk,reset,enable : IN std_logic; count :OUT std_logic_vector(3 downto 0);END count;ARCHITECTURE counter OF count IS SIGNAL count_int:std_logic_vector(0 to 3); BEGIN PROCESS(clk,reset) BEGIN WAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (
31、OTHERS => '0');ELSIF enable = '1' THEN IF(count_int="1001") THEN count_int<="0000"文档大全实用标准文案ELSEcount_int <= count_int 1;-ELSE- -NULL ;- -IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;-
32、-IF (reset='0') then-q<="0000"- -ELSIF(clk'event and clk='1') THEN- -q<=q 1;- -IF (q<="1001") then-q<="0000"- -END IF;- -IF (reset<='1')THEN-q<="00"-ELSIF- -wait until (clk'event and clk='1');- -WAIT UN
33、TIL (clk'EVENT AND clk = '1');文档大全实用标准文案- -WAIT UNTIL (clock'EVENT AND- -q<=q '1'- -end if;- -count<=q;- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then- -WAIT UNTIL rising_edge(clock);- -clock'event and clock='1'- -count <
34、;= 0;clock = '1');-WAIT UNTIL (clock'EVENT AND-WAIT riseedge clock = '1'clock = '1');-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND-WAIT UNTIL clock = '1'clock = '1');-if (cloc
35、k'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;文档大全实用标准文案- -END PROCESS;END counter;九计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY ninecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_
36、ve ctor(3 downto 0);END ninecout;ARCHITECTURE counter OF ninecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1000") TH
37、ENcount_int<="0000"文档大全实用标准文案ELSEcount_int <= count_int 1;-ELSE- -NULL ;- -IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- -IF (reset='0') then-q<="0000"- -ELSIF(clk'event and clk='1'
38、;) THEN- -q<=q 1;- -IF (q<="1001") then-q<="0000"- -END IF;- -IF (reset<='1')THEN-q<="00"-ELSIF- -wait until (clk'event and clk='1');- -WAIT UNTIL (clk'EVENT AND clk = '1');文档大全实用标准文案- -WAIT UNTIL (clock'EVENT AND- -q&l
39、t;=q '1'- -end if;- -count<=q;- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then- -WAIT UNTIL rising_edge(clock);- -clock'event and clock='1'- -count <= 0;clock = '1');-WAIT UNTIL (clock'EVENT AND-WAIT riseedge clock = '1'
40、clock = '1');-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND-WAIT UNTIL clock = '1'clock = '1');-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;
41、-end if;-end if;文档大全实用标准文案- -END PROCESS;END counter;八计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY eightcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_ve ctor(2 downto 0);END eightcout;ARCHITECTURE counter OF eightcout ISSIGNAL count_int:std_
42、logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="111") THENcount_int<="000"文档大全实用标准文案ELSEcount_int <= count_int 1;-ELSE- -NULL ;- -
43、IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- -IF (reset='0') then-q<="0000"- -ELSIF(clk'event and clk='1') THEN- -q<=q 1;- -IF (q<="1001") then-q<="0000"- -END IF;- -
44、IF (reset<='1')THEN-q<="00"-ELSIF- -wait until (clk'event and clk='1');- -WAIT UNTIL (clk'EVENT AND clk = '1');文档大全实用标准文案- -WAIT UNTIL (clock'EVENT AND- -q<=q '1'- -end if;- -count<=q;- -WAIT UNTIL clock = '1'- -if (clock'
45、event and clock='1')then- -WAIT UNTIL rising_edge(clock);- -clock'event and clock='1'- -count <= 0;clock = '1');-WAIT UNTIL (clock'EVENT AND-WAIT riseedge clock = '1'clock = '1');-if (clock'event and clock='1') then-WAIT UNTIL rising_edg
46、e(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND-WAIT UNTIL clock = '1'clock = '1');-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;文档大全实用标准文案- -END PROCESS;END counter;六计数器library ieee;use ieee.std_logic_11
47、64.all;use ieee.std_logic_unsigned.all;ENTITY sixcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_ve ctor(2 downto 0);END sixcout;ARCHITECTURE counter OF sixcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1
48、9; THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THEN文档大全实用标准文案IF(count_int="101") THENcount_int<="000"ELSEcount_int <= count_int 1;-ELSE- -NULL ;- -IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;coun
49、t <= count_int;- -IF (reset='0') then-q<="0000"- -ELSIF(clk'event and clk='1') THEN- -q<=q 1;- -IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF文档大全实用标准文案-wait until (clk'event and clk
50、='1');- -WAIT UNTIL (clk'EVENT AND clk = '1');- -WAIT UNTIL (clock'EVENT AND clock = '1');- -q<=q '1'- -end if;- -count<=q;- -WAIT UNTIL clock = '1'- -if (clock'event and clock='1')then- -WAIT UNTIL rising_edge(clock);- -clock'eve
51、nt and clock='1'- -count <= 0;- -WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'eventand clock='1') then-WAITUNTILrising_edge(clock);-count<=1;-WAITUNTIL(clock'EVENT ANDclock ='1');-WAITUNTILclock = '1'-if (clock'eventand clock='1')then-WAIT UNTILrising_edge(clock);-count <= 2;-end if;文档大全实用标准文案- -end if;- -end if;- -END PRO
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