杭电计组实验4-寄存器堆设计实验

1、实验报告成绩:2018年 5月 12 日姓名阳光男学号班级专业计算机科学与技术课程名称计算机组成原理与系统结构试验任课老师张翔老师指导老师张翔老师机位号默认实验序号实验名称实验四寄存器堆设计实验时间2018/5/12实验地点1 教 211实验设备号个人电脑、Nexys3开发板、实验程序源代码1. 寄存器堆模块代码：module Register；inp ut 4:0R_Addr_A;inp ut 4:0R_Addr_B;inp ut 4:0W_Addr;input Write_Reg;inp ut 31:0W_Data;input Clk;input Reset;out put 31:0R_D

2、ata_A;out put 31:0R_Data_B;reg 31:0REG_Files0:31;reg 5:0i;initial/仿真过程中的初始化 beginfor(i=0;i<=31;i=i+1)REG_Filesi=0;endassign R_Data_A=REG_FilesR_Addr_A; assign R_Data_B=REG_FilesR_Addr_B; always (po sedge Clk or po sedge Reset) beginif(Reset)for(i=0;iv=31;i二i+1) REG_Filesi=O; else if(Write_Reg&

3、;&W_Addr!=O) REG_FilesW_Addr二W_Data; end en dmodule2. 顶层电路模块代码：module Top_Register_);inp ut 4:0Addr;input 1:0C1;/C1选择32位数据输出哪八位字节input Write_Reg,C2,Clk,Reset;/C2选择读 A/B 端口的数据out put reg 7:0LED;wire 31:0R_Data_A,R_Data_B;reg 31:0W_Data;reg4:0 A,B;Register_(A,B,Addr,Write_Reg,W_Data,Clk,Reset,R_Da

4、ta_A,R_Data_B); always(Addr or Write_Reg or C1 or C2 or R_Data_A or R_Data_B) beginA=0;B=0;LED=0;W_Data=0;if(!Write_Reg)/ 读操作 Write_Reg=0beginif(!C2)begi nA=Addr;case(C1)2'b00:LED=R_Data_A7:0;2'b01:LED=R_Data_A15:8;2'b10:LED=R_Data_A23:16;2'b11:LED二R Data A31:24;endcaseendelsebeginB=

5、Addr;case(C1)2'b00:LED=R_Data_B7:0; 2'b01:LED=R_Data_B15:8; 2'b10:LED=R_Data_B23:16; 2'b11:LED=R_Data_B31:24;endcaseendendelse/写操作beg incase(C1)2'b00:W_Data=32'h0000_0003;2'b01:W_Data=32'h0000_0607;2'b10:W_Data=32'hFFFF_FFFF;2'b11:W_Data=32'h1111_1234;

6、 endcaseendenden dmodule3. 测试代码module test;/I nputsreg 4:0 R_Addr_A; reg 4:0 R_Addr_B;reg 4:0 W_Addr; reg Write_Reg;reg 31:0 W Data;reg Clk; reg Reset;/ Out putswire 31:0 R_Data_A; wire 31:0 R_Data_B;/ I nsta ntiate the Unit Un der Test (UUT) Register_ (.R_Addr_A(R_Addr_A),.R_Addr_B(R_Addr_B), .W_Ad

7、dr(W_Addr), .Write_Reg(Write_Reg), .W_Data(W_Data), .Clk(Clk),只 eset(Reset),.R_Data_A(R_Data_A), .R_Data_B(R_Data_B);in itial begi n/In itialize Inputs R_Addr_A = 0; R_Addr_B = 0;W_Addr = 0; Write_Reg = 0;W_Data = 0; Clk = 0;Reset = 0;/ Wait 100 ns for global reset to finish #100;/ Add stimulus here

8、#100;R_Addr_A = 0;R_Addr_B = 0; W_Addr = 5'b00001;Write_Reg = 1;W_Data = 32'h1111_1111; Clk = 1;Reset = 0;#100;R_Addr_A = 0;R_Addr_B = 0;W_Addr = 5'b00001;Write_Reg = 1;W_Data = 32'h1111_1111; Clk = 0;Reset = 0;#100;R_Addr_A = 0;R_Addr_B = 0;W_Addr = 5'b00010;Write_Reg = 1;W_Data

9、 = 32'h2222_2222;Clk = 1;Reset = 0;#100;R_Addr_A = 5'b00001; R_Addr_B = 5'b00010; W_Addr = 0;Write_Reg = 0;W_Data = 0;Clk = 0;Reset 二 0;#100;R_Addr_A = 5'b00001;R_Addr_B = 5'b00010;W_Addr = 0;Write_Reg = 0;W_Data = 0;Clk = 0;Reset = 1;end en dmodule、仿真波形» RJ s.s-iiAi'd L

10、i' A h 孔如卩笳MWt V R_3 4|E：CL0：fr *_*ikH-D：0：n> 书 w_Dit<M e.OyDDDaO-：巒AndRil】n裕I盘0和>K fliI shh.iihi lr hfcJlJBffi i iJJj aOfnefiWj I55-i-luSlii*目 it-I&I& nfehSlI =HI鬲 u .pn .25$®51；R茴：j-三、电路图顶层电路模块Top_Regiister_filerA曲r(4 0)-、一 LZD(7 01C1(1 Oi _CIhC2ResetWrttB_Reg *LTop_Regis

11、ter_file顶层电路内部结构:taw Ai cm n tA 口 I m -訂GF71-?Myi_LC01-CT 11 n. Ap I MH Ml di-C 11#;: yjL"'. A"-*'_?T'L：'rL"*-i_WTi1 *.(WM厂rdHn>9十亠HM -> *me Me帚,.V)-A四、引脚配置（约束文件）NET "Clk" LOC = C9;NET "Reset" LOC = D9;NET "Write_Reg" LOC = T5;NET &q

12、uot;C2" LOC = C4;# Plan Ahead Gen erated p hysical con stra intsNET "LED7" LOC = T11;NET "LED6" LOC = R11;NET "LED4" LOC = M11;NET "LED3" LOC = V15;NET "LED1" LOC = V16;NET "LED0" LOC = U16;NET "LED2" LOC = U15;NET "LED5

13、" LOC = N11;NET "Addr0" LOC = T10;NET "Addr2" LOC = V9;NET "Addr3" LOC = M8;NET "Addr4" LOC = N8;NET "C10" LOC = U8;NET "C11" LOC = V8;NET "Addr1" LOC = T9;五、思考与探索(1)实验四实验结果记录表寄存器地址写入数据读出数据$132'h0000_000332'h0000_0003$232'h0000_060732'h0000_0607$332'