出租车计费器设计(部分)

1、页眉.出租车计费器出租车的出现给人们的生活带来了极大的便利，日渐成为城市交通工具中重要的成员之一。本实验以日常所见的出租车计费器为设计目标，实现其计程、计时、预置、计费等功能。一、系统设计要求设计一个满足日常生活所需功能的出租车计费器。该计费器能实现计费功能。车起步开始计费，首先显示起步价，起步费为 3.00 元，车在行驶 3KM 以内，只收起步价。车行驶超过 3KM 之后，没 KM2 元，车费依次累加。当总费用达到或超过 40 元时，每 KM 收费 4 元。当遇到红灯或客户需要停车等待时，则按时间计费，计费单价为每 20s 收费 1 元。实现计费器预置功能， 能够预置起步费、 每公里收费、

2、车行加费里程、 计时收费等。可以模拟汽车行驶、停止、暂停等状态，并根据不同状态进行计费。以十进制显示出租车行驶路程与车费。二、系统设计方案分析系统设计要求不难得知，整个出租车计费系统按功能主要分为速度模块、计程模块、计时模块和计费模块。速度模块：通过对速度信号sp 的判断，决定变量kinside 的值。 kinside 即是进行100m 所需要的时钟周期数，然后每行进100m，则产生一个脉冲clkout 。计程模块：由于一个 clkout 信号代表行进 100m，故通过对 clkout 计数，可以获得共行进的距离 kmcount。计时模块：在汽车启动后，当遇到顾客等人或红灯时， 出租车采用计时

3、收费的方式。通过对速度信号 sp 的判断决定是否开始记录时间。当 sp=0 时，开始记录时间。当时间达到足够长时则产生timecount 脉冲，并重新计时。一个timecount 脉冲相当于等待的时间达到了时间计费的长度。这里选择系统时钟频率为500HZ， 20s 即计数值为 1000。计费模块由两个进程组成。其中，一个进程根据条件对enable 和 price 赋值：当记录的距离达到 3 公里后 enable 变为 1，开始进行每公里收费，当总费用大于40 元，则单价 price 由原来的 2 元每公里变为 4 元每公里；第二个进程在每个时钟周期判断 timecount 和 clkout 的

4、值。当其为 1 时，则在总费用上加上相应的费用。三、VHDL 编程速度模块的 VHDL 代码如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;1 / 9页眉.ENTITY speed ISPORT (clk : IN STD_LOGIC;reset : IN STD_LOGIC;start: IN STD_LOGIC;stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);clkout: OUT STD_LOGIC;);END speed;

5、ARCHITECTURE rtl OF speed ISBEGINPROCESS (clk, reset, stop, start, sp)TYPE state_type IS (s0,s1);VARIABLE s_state: state_type;VARIABLE cnt: integer range 0 to 28;VARIABLE kinside: integer range 0 to 30;BEGINCASE sp ISWHEN “000”=>kinside :=0;WHEN “001”=>kinside :=28;WHEN “010”=>kinside :=24;

6、WHEN “011”=>kinside :=20;WHEN “100”=>kinside :=16;WHEN “101”=>kinside :=12;WHEN “110”=>kinside :=8;WHEN “111”=>kinside :=4;END CASE;IF reset=1THENs_state:=s0;ELSIF (rising_edge(clk) thenCASE s_state isWHEN s0=>2 / 9页眉.cnt:=0;clkout<= 0;IF start=1THEN s_state:=s1;ELSE s_state:=s0

7、;END IF;WHEN s1=>Clkout<= 0;IF (stop=1)THENs_state<=s0;ELSIF sp=”000”then s_state:=s1;ELSIF cnt=kinside thencnt:=0; clkout<= 1;s_state:=s1;ELSE cnt:=cnt+1;s_state:=s1;END IF;END CASE;END IF;END PROCESS;END rtl;计程模块的 VHDL 代码如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UN

8、SIGNED.ALL;ENTITY kilometers ISPORT (clkout, reset : IN STD_LOGIC;kmcnt1,kmcnt2,kmcnt3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END kilometers;ARCHITECTURE rtl OF kilometers ISBEGINPROCESS (clkout, reset)3 / 9页眉.VARIABLE km_reg: STD_LOGIC_VECTOR(11 DOWNTO 0); BEGINIF reset=1THENkm_reg:=”000000000000”;ELSIF

9、 (rising_edge(clkout) thenIF km_reg(3 DOWNTO 0)= ”1001”THENkm_reg := km_reg +”0111”;ELSE km_reg(3 DOWNTO 0)= km_reg(3 DOWNTO 0)+ ”0001”; END IF;IF km_reg(7 DOWNTO 4)= ”1010”THENkm_reg := km_reg +”01100000”;END IF;END IF;kmcnt1<=km_reg(3 DOWNTO 0);kmcnt2<=km_reg(7 DOWNTO 4);kmcnt3<=km_reg(11

10、 DOWNTO 8);END PROCESS;END rtl;计时模块的 VHDL 代码如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY times ISPORT (clk : IN STD_LOGIC;reset : IN STD_LOGIC;start: IN STD_LOGIC;stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);timecount: OUT STD_LOGIC;);END times;4 / 9页眉

11、.ARCHITECTURE rtl OF times ISBEGINPROCESS (clk, reset, stop, start, sp)TYPE state_type IS (t0,t1,t2);VARIABLE t_state: state_type;VARIABLE cnt: integer range 0 to 28;VARIABLE waittime: integer range 0 to 1000;BEGINIF reset=1THENt_state:=t0;ELSIF (rising_edge(clk) thenCASE t_state isWHEN t0=>waitt

12、ime:=0;timecount<=0;IF start=1THEN t_state:=t1;ELSE t_state:=t0;END IF;WHEN t1=>IF (sp=”000”) THENt_state:=t2;ELSE waittime:=0;t_state:=t1;END IF;WHEN t2=>waittime:= waittime +1;timecount<=0;IF waittime <=1000 THENwaittime:=0;timecount<=1;ELSIF stop=1then t_state:=t0;ELSIF sp=”000”

13、thent_state:=t2;ELSE timecount<=0;5 / 9页眉.t_state:=t1;END IF;END CASE;END IF;END PROCESS;END rtl;计费模块的 VHDL 代码如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY kmmoney ISPORT (clk, reset, timecount, clkout: IN STD_LOGIC;kmcnt2, kmcnt3, count1, count2, count3: OUT

14、STD_LOGIC_VECTOR(3 DOWNTO 0);END kmmoney;ARCHITECTURE rtl OF kmmoney ISSIGNAL cash: STD_LOGIC_VECTOR(11 DOWNTO 0);SIGNAL price: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL enable: STD_LOGIC;BEGINkmmoney 1: PROCESS (cash,kmcnt2)BEGINIF reset=1THENcash<=”000000000011”;ELSIF (rising_edge(clk) thenIF timecou

15、nt=1THENreg2:<=cash;IF reg2(3 DOWNTO 0)+ ”0001”>”1001”THENreg2(7 DOWNTO 0) := reg2( 7 DOWNTO 0)+ ”00000111”; IF reg2(7 DOWNTO 4) > ”1001”THEN6 / 9页眉.cash<=reg2+”000001100000”;ELSE cash<=reg2+”0001”;END IF;ELSIF (clkout= 1)and (enable=1)THENIF clkout_cnt=9 THENclkout_cnt:=0;reg2:=cash;

16、IF “0000”&reg2(3 DOWNTO 0)+price(3 DOWNTO 0)>”00001001” THEN reg2(7 DOWNTO 0):=reg2(7 DOWNTO 0)+ ”00000110”+price;IF reg2(7 DOWNTO 4) > ”1001”THEN cash<=reg2+”000001100000”;ELSEcash<=reg2;END IF;ELSEcash<=reg2+price;END IF;ELSEclkout_cnt:=clkout_cnt+1;END IF;END IF;END IF;END PROC

17、ESS;count1<=cash(3 DOWNTO 0);count2<=cash(7 DOWNTO 4);count3<=cash(11 DOWNTO 8);END rtl;顶层模块的 VHDL 代码如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY top ISPORT (clk, reset, start, stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);7 / 9页眉.kmcnt1,kmcnt2,kmcnt3,count1,count2,count3: OU

18、T STD_LOGIC_VECTOR(3 DOWNTO 0);END top;ARCHITECTURE rtl OF top ISComponent speed isPORT (clk : IN STD_LOGIC;reset : IN STD_LOGIC;start: IN STD_LOGIC;stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);clkout: OUT STD_LOGIC;);End Component speed;Component times isPORT (clk : IN STD_LOGIC;reset : I

19、N STD_LOGIC;start: IN STD_LOGIC;stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);timecount: OUT STD_LOGIC;);End Component times;Component kilometers isPORT (clkout, reset : IN STD_LOGIC;kmcnt1,kmcnt2,kmcnt3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);End Component kilometers;Component kmmoney isPORT (clk, reset