Lecture5简单数字电路设计-组合电路课件

1、Lecture5简单数字电路设计-组合电路Verilog HDL语言语言华中科技大学计算机华中科技大学计算机科学与技术科学与技术学院学院主讲：胡迪青主讲：胡迪青Email: QQ: 121374333Lecture5简单数字电路设计-组合电路2简单数字电路设计简单数字电路设计Lecture5简单数字电路设计-组合电路3设计验证与仿真设计验证与仿真qVerilog HDL不仅提供描述设计的能力，而且提供对激励、不仅提供描述设计的能力，而且提供对激励、控制、存储响应和设计验证的建模能力。控制、存储响应和设计验证的建模能力。q激励和控制可用初始化语句产生。验证运行过程中的响应可激励和控制可用初始化语

2、句产生。验证运行过程中的响应可以作为以作为“变化时保存变化时保存”或作为选通的数据存储。或作为选通的数据存储。q最后，设计验证可以通过在初始化语句中写入相应的语句自最后，设计验证可以通过在初始化语句中写入相应的语句自动与期望的响应值比较完成。动与期望的响应值比较完成。q要测试一个设计块是否正确，就要用要测试一个设计块是否正确，就要用Verilog再写一个测试模再写一个测试模块。这个测试模块应包括以下三个方面的内容：块。这个测试模块应包括以下三个方面的内容：测试模块中要调用到设计块，只有这样才能对它进行测试；测试模块中要调用到设计块，只有这样才能对它进行测试；测试模块中应包含测试的激励信号源；测

3、试模块中应包含测试的激励信号源；测试模块能够实施对输出信号的检测，并报告检测结果。测试模块能够实施对输出信号的检测，并报告检测结果。Lecture5简单数字电路设计-组合电路4Simulating/Validating HDL The sad truth 10% design, 90% validation If you do it right you will spend 9X more time testing/validating a design than designing it.DesignUnder Test(verilog)StimulusGeneration(verilog)

4、OutputMonitoringSelf Checking(verilog)filefileVerilog test bench shellTestbenchs are written in verilog as well. Testbench verilog is not describing hardware and can be thought of as more of a program.Lecture5简单数字电路设计-组合电路5Testbench Example (contrived but valid)module test_and;integer file, i, code;

5、reg a, b, expect, clock;wire out;parameter cycle = 20;and #4 a0(out, a, b); / Circuit under testinitial begin : clock = 0; file = $fopen(compare.txt, “r” ); for (i = 0; i 4; i=i+1) begin (posedge clock) / Read stimulus on rising clock code = $fscanf(file, %b %b %bn, a, b, expect); #(cycle - 1) / Com

6、pare just before end of cycle if (expect != out) $strobe(%d %b %b %b %b, $time, a, b, expect, out); end / for $fclose(file); $stop; end / initialalways #(cycle /2) clock = clock; / Clock generatorendmoduleLecture5简单数字电路设计-组合电路6组合逻辑设计组合逻辑设计q组合逻辑电路组合逻辑电路 可以有若个输入变量和若干个输出变量，其每个输出变量是其输入的逻可以有若个输入变量和若干个输出变

7、量，其每个输出变量是其输入的逻辑函数，其每个时刻的输出变量的状态仅与当时的输入变量的状态有关，辑函数，其每个时刻的输出变量的状态仅与当时的输入变量的状态有关，与本输出的原来状态及输入的原状态无关，也就是与本输出的原来状态及输入的原状态无关，也就是输入状态的变化立即输入状态的变化立即反映在输出状态的变化反映在输出状态的变化。q逻辑电路的各种运算可以用布尔代数来描述逻辑电路的各种运算可以用布尔代数来描述q狄摩根定律狄摩根定律利用狄摩根（利用狄摩根（DeMorgan）定律可以将积之和形式的电路转换为和之）定律可以将积之和形式的电路转换为和之积形式的电路，或反之。积形式的电路，或反之。Lecture5

8、简单数字电路设计-组合电路7q组合逻辑的三种通用表示方法组合逻辑的三种通用表示方法结构化（即门级）原理图结构化（即门级）原理图真值表真值表布尔方程式布尔方程式q实例：半加器实例：半加器二进制输入二进制输入和输出和输出进位输出进位输出basco0000011010101101sa bababcoa bLecture5简单数字电路设计-组合电路8Combinational CircuitsComponent InstantiationsCircuit A connection of modules Also known as structure A circuit is a second way

9、to describe amodule vs. using an always procedure, as earlierInstance An occurrence of a module in acircuit May be multiple instances of a module e.g., Cars modules: tires, engine, windows,etc., with 4 tire instances, 1 engine instance,6 window instances, etc.Lecture5简单数字电路设计-组合电路9Combinational Circ

10、uitsModule InstantiationsLecture5简单数字电路设计-组合电路10Combinational CircuitsModule InstantiationsLecture5简单数字电路设计-组合电路11Combinational CircuitsModule InstantiationsLecture5简单数字电路设计-组合电路12Combinational Circuit StructureSimulatingg the CircuitSame testbench format for BeltWarnmodule as for earlier And2 modul

11、eLecture5简单数字电路设计-组合电路13Combinational Circuit StructureSimulatingg the CircuitLecture5简单数字电路设计-组合电路14Combinational Circuit StructureSimulatingg the Circuittimescale 1 ns/1 nsmodule Testbench();reg K_s, P_s, S_s;wire W_s;BeltWarn CompToTest(K_s, P_s, S_s, W_s);initial beginMore on testbenches Note th

12、at a single module instantiationstatement used reg and wire declarations (K_s, P_s,S_s, W_s) used because procedurecannot access instantiated modules= 0; S_sP_s = 1;P_s = 1;P_s = 1;= 0;S_s = 0;S_s = 0;S_s = 1;K_s = 0; P_s#10 K_s = 0;#10 K_s = 1;#10 K_s = 1;endendmoduleports directly Inputs declared

13、as regs so can assignvalues (which are held betweenassignments) Note module instantiation statementand procedure can both appear in onemoduleLecture5简单数字电路设计-组合电路15Combinational Behavior to StructureLecture5简单数字电路设计-组合电路16Combinational Behavior to StructureAlways Procedures with Assignment Statement

14、sLecture5简单数字电路设计-组合电路17Combinational Behavior to StructureProcedures with Assignment StatementsProcedural assignment statement Assigns value to variable Right side may be expression ofoperatorstimescale 1 ns/1 nsmodule BeltWarn(K, P, S, W);input K, P, S;output W;reg W; Built-in bit operators includ

15、e& AND | OR NOTXORXNORalways (K, P, S) beginW = K & P & S;endendmodule Q: Create an always procedure tocompute: F = CH + CHAnswer 1:always (C,H) beginF = (C&H) | (C&H);endAnswer 2:always (C,H)beginF = C H;endLecture5简单数字电路设计-组合电路18Combinational Behavior to StructureProcedures wit

16、h Assignment StatementsProcedure may have multipleassignment statementstimescale 1 ns/1 nsmodule TwoOutputEx(A, B, C, F, G);input A, B, C;output FF, G;reg F, G;always (A, B, C) beginF = (B & B) | C;G = (A & B) | (B & C);endendmoduleLecture5简单数字电路设计-组合电路19Combinational Behavior to Structu

17、reProcedures with If-Else StatementsProcess may use if-else statements(a.k.a. conditional statements) if (expression) If expression is true (evaluates tononzero value), executecorresponding statement(s) If false (evaluates to 0), executeelsess statement (else part isoptional) Example shows use of op

18、erator =timescale 1 ns/1 nsmodule BeltWarn(K, P, S, W);input K, P, S;output W;reg W;always (K, P, S) beginif (K & P & S) = 1)W = 1;elseW = 0;logical equality, returns true/false(actually, returns 1 or 0)endendmodule True is nonzero value, false is zeroLecture5简单数字电路设计-组合电路20Combinational Beh

19、avior to StructureProcedures with If-Else StatementsMore than two possibilities Handled by stringing if-elsestatements together Known as if-else-if constructExample: 4x1 mux behaviortimescale 1 ns/1 nsmodule Mux4(I3, I2, I1, I0, S1, S0, D);input I3, I2, I1, I0;input S1, S0;output D;SupposeS1S0change

20、 to01 Suppose S1S0 change to 01 ifs expression is false elses statement executes,which is an if statementwhose expression is truereg D;always (I3, I2, I1, I0, S1, S0)beginif (S1=0 & S0=0)D = I0;else if (S1=0 & S0=1)D = I1;else if (S1=1 & S0=0)D = I2;elseD = I3;Note: The following indenta

21、tion shows ifstatement nesting, but is unconventional:if (S1=0 & S0=0)endendmoduleD = I0;elseif (S1=0 & S0=1)D = I1;else&logical AND& : bit AND (operands are bits, returns bit)& : logical AND (operands are true/falseif (S1=1 & S0=0)D = I2;elseD = I3;values, returns true/false

22、)Lecture5简单数字电路设计-组合电路21Combinational Behavior to StructureProcedures with If-Else StatementsLecture5简单数字电路设计-组合电路22Combinational Behavior to StructureLecture5简单数字电路设计-组合电路23Combinational Behavior to StructureCommon Pitfall Missing Inputs from Event Control ExpressionLecture5简单数字电路设计-组合电路24Combinati

23、onal Behavior to StructureCommon Pitfall Missing Inputs from Event Control ExpressionVerilog provides mechanism to help avoidthis pitfall * implicit event control expression Automatically adds all nets and variablesthat are read by the controlled statement orstatement group Thus, * in example is equivalent to(S1,S0,I0,I1,I2,I3)timescale 1 ns/1 nsmodule Mux4(I3, I2, I1,