八位加法器设计实验报告

1、实验四：8位加法器设计实验1.实验目的：熟悉利用quartus原理图输入方法设计简单组合电路，掌握层次化设计方法。2.实验原理：一个八位加法器可以由八个全加器构成，加法器间的进位可以串行方式实现，即将低位加法器的进位输出cout与相邻的高位加法器的最低进位输入信号cin相接。3.实验任务：完成半加器，全加器，八位加法器设计，使用例化语句，并将其设计成一个原件符号入库，做好程序设计，编译，程序仿真。1）编译成功的半加器程序：module h_adder(a,b,so,co);input a,b;output so,co;assign so=ab;assign co=a&b; endmodule2

2、）编译成功的全加器程序：module f_adder(ain,bin,cin,cout,sum); output cout,sum;input ain,bin,cin; wire net1,net2,net3; h_adder u1(ain,bin,net1,net2); h_adder u2(.a(net1),.so(sum),.b(cin),.co(net3); or u3(cout,net2,net3);endmodule3）编译成功的八位加法器程序：module f_adder8(ain,bin,cin,cout,sum); output 7:0sum; output cout;inp

3、ut 7:0ain,bin;input cin;wire cout0, cout1, cout2 ,cout3, cout4,cout5,cout6;f_adder u0(.ain(ain0),.bin(bin0),.cin(cin),.sum(sum0),.cout(cout0);f_adder u1(.ain(ain1),.bin(bin1),.cin(cout0),.sum(sum1),.cout(cout1); f_adder u2(.ain(ain2),.bin(bin2),.cin(cout1),.sum(sum2),.cout(cout2);f_adder u3(.ain(ain

4、3),.bin(bin3),.cin(cout2),.sum(sum3),.cout(cout3);f_adder u4(.ain(ain4),.bin(bin4),.cin(cout3),.sum(sum4),.cout(cout4);f_adder u5(.ain(ain5),.bin(bin5),.cin(cout4),.sum(sum5),.cout(cout5);f_adder u6(.ain(ain6),.bin(bin6),.cin(cout5),.sum(sum6),.cout(cout6);f_adder u7(.ain(ain7),.bin(bin7),.cin(cout6

5、),.sum(sum7),.cout(cout);endmodule4）八位加法器仿真程序：module f_adder8_vlg_tst();/ constants / general purpose registers/reg eachvec;/ test vector input registersreg 7:0 ain;reg 7:0 bin;reg cin;/ wires wire cout;wire 7:0 sum;/ assign statements (if any) f_adder8 i1 (/ port map - connection between master ports and signals/registers .ain(ain),.bin(bin),.cin(cin),.cout(cout),.sum(sum);initial begin ain=10;bin=11;cin=0;#100 ain=10;bin=10;cin=0;#100 ain=10;bin=10;cin=1;#100 ain=12;bin=18;cin=0;#100 ain=12;bin=18;cin=1;#100 $s