VHDL时钟程序--精选文档

1、library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Counter_m_f_s isport (clk,reset : in std_logic ;bcd_h_m: out std_logic_vector(3 downto 0); -秒钟个位输出bcd_l_m: out std_logic_vector(3 downto 0); -秒钟十位输出bcd_l_f: out std_logic_vector(3 downto 0); -分钟个位输出bcd_h_f: out std_logic

2、_vector(3 downto 0); -分钟十位输出bcd_l_s: out std_logic_vector(3 downto 0); -时钟个位输出bcd_h_s: out std_logic_vector(3 downto 0); -时钟十位输出up : out std_logic);end Counter_m_f_s ;architecture behav of Counter_m_f_s issignal bcd_h_m_r : std_logic_vector(3 downto 0); -秒钟个位内部信号signal bcd_l_m_r : std_logic_vector(3

3、 downto 0); -秒钟十位内部信号signal bcd_h_f_r : std_logic_vector(3 downto 0); -分钟个位内部信号signal bcd_l_f_r : std_logic_vector(3 downto 0); -分钟十位内部信号signal bcd_h_s_r : std_logic_vector(3 downto 0); -时钟个位内部信号signal bcd_l_s_r : std_logic_vector(3 downto 0); -时钟个位内部信号signal up_r1 : std_logic;signal up_r2 : std_log

4、ic;beginU1: process (clk, reset) -秒钟 begin if reset='0' then bcd_h_m_r <="0000" bcd_l_m_r <="0000" up_r1 <='0'else if clk'event and clk='1' then if bcd_h_m_r ="0101" and bcd_l_m_r ="1001" then bcd_h_m_r <="0000"

5、; -59秒，分钟进一 bcd_l_m_r <="0000" up_r1 <= '1' ; else if bcd_l_m_r(3 downto 0) = "1001" then -秒的个位为9，十位进一，分钟不进为 bcd_l_m_r(3 downto 0)<= "0000" ; bcd_h_m_r(3 downto 0) <= bcd_h_m_r(3 downto 0) + 1 ; up_r1 <= '0' else bcd_l_m_r(3 downto 0) <

6、= bcd_l_m_r(3 downto 0) + 1 ; up_r1 <= '0' end if; end if; end if; end if; end process;bcd_h_m <= bcd_h_m_r;bcd_l_m <= bcd_l_m_r;U2: process (up_r1 , reset) -分钟 beginif reset='0' then bcd_h_f_r <="0000" bcd_l_f_r <="0000" up_r2 <='0'else

7、if up_r1'event and up_r1='1' then if bcd_h_f_r ="0101" and bcd_l_f_r ="1001" then -59分，时钟进一 bcd_h_f_r <="0000" bcd_l_f_r <="0000" up_r2 <= '1' ; else if bcd_l_f_r(3 downto 0) = "1001" then -分的个位为9，十位进一，时钟不进位 bcd_l_f_r(3 d

8、ownto 0) <= "0000" ; bcd_h_f_r(3 downto 0) <= bcd_h_f_r(3 downto 0) + 1 ; up_r2 <= '0' else bcd_l_f_r(3 downto 0) <= bcd_l_f_r(3 downto 0) + 1 ; up_r2 <= '0' end if; end if; end if; end if; end process;bcd_h_f <= bcd_h_f_r;bcd_l_f <= bcd_l_f_r; U3: proc

9、ess ( up_r2 , reset) 时钟beginif reset='0' then bcd_h_s_r <="0000" bcd_l_s_r <="0000" up <='0'else if up_r2'event and up_r2='1' then if bcd_h_s_r ="0010" and bcd_l_s_r ="0011" then -23时，时钟进一。 bcd_h_s_r <="0000" b

10、cd_l_s_r <="0000" up <= '1' ; else if bcd_l_s_r(3 downto 0) = "1001" then bcd_l_s_r(3 downto 0)<= "0000" ; bcd_h_s_r(3 downto 0) <= bcd_h_s_r(3 downto 0) + 1 ; up <= '0' else bcd_l_s_r(3 downto 0) <= bcd_l_s_r(3 downto 0) + 1 ; up <=

11、 '0' end if; end if; end if; end if; end process;bcd_h_s <= bcd_h_s_r;bcd_l_s <= bcd_l_s_r; end architecture behav; 另外给大家数码管的驱动程序！LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_Unsigned.ALL;ENTITY showseg7 IS PORT(clk: IN STD_LOGIC;-d:in std_logic_vector(31 downto 0); seg0

12、,seg1,seg2,seg3,seg4,seg5,seg6,seg7,dig0,dig1,dig2,dig3,dig4,dig5,dig6,dig7:OUT STD_LOGIC );END ENTITY showseg7;ARCHITECTURE one OF showseg7 IS SIGNAL count: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL seg_r: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL dig_r: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL data: STD_LOGIC_V

13、ECTOR(31 DOWNTO 0); SIGNAL disp_r: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINdata <= "00000001001000110100010101100111"-d;-这是一个接口，存放要显示的数据 PROCESS(clk) -1kHz BEGIN IF clk'EVENT AND clk='1' THEN IF count<=7 THEN count<=count+1; ELSE count<="000" END IF; END IF; END

14、 PROCESS; PROCESS(count) BEGIN CASE count IS WHEN "000" => disp_r<=data(31 DOWNTO 28);dig_r<="01111111"-"00000000"- WHEN "001" => disp_r<=data(27 DOWNTO 24);dig_r<="10111111"-"00000000"- WHEN "010" => disp_r&l

15、t;=data(23 DOWNTO 20);dig_r<="11011111"-"00000000"- WHEN "011" => disp_r<=data(19 DOWNTO 16);dig_r<="11101111"-"00000000"- WHEN "100" => disp_r<=data(15 DOWNTO 12);dig_r<="11110111"-"00000000"- WHEN

16、"101" => disp_r<=data(11 DOWNTO 8);dig_r<="11111011"-"00000000"- WHEN "110" => disp_r<=data(7 DOWNTO 4);dig_r<="11111101"-"00000000"- WHEN "111" => disp_r<=data(3 DOWNTO 0);dig_r<="11111110"-&q

17、uot;00000000"- WHEN OTHERS => NULL; END CASE; END PROCESS; PROCESS(disp_r) BEGIN CASE disp_r IS WHEN "0000" => seg_r<="11000000"-"10000001" WHEN "0001" => seg_r<="11111001"-"11111001" WHEN "0010" => seg_r<

18、;="10100100"-"10110001" WHEN "0011" => seg_r<="10110000"-"11000010" WHEN "0100" => seg_r<="10011001"-"11011000" WHEN "0101" => seg_r<="10010010"-"10100100" WHEN "0110&

19、quot; => seg_r<="10000011"-"10100000" WHEN "0111" => seg_r<="11111000"-"10001111" WHEN "1000" => seg_r<="10000000"-"10000000" WHEN "1001" => seg_r<="10010000"-"10000100"- WHEN "1010" => seg_r<