verilog编写的1024点的fft快速傅立叶变换代码[最新]

1、verilog 编写的 1024 点的 fft 快速傅立叶变换代码最新 1024点的fft 快速傅立叶变换 verilog 代码'timescale 1 ns / 1 nsmodule cf_fft_1024_8 (clock_c, enable_i, reset_i, sync_i, data_0_i,data_1_i, sync_o,data_0_o, data_1_o); input clock_c; input enable_i; input reset_i;input sync_i;input 15:0 data_0_i; input 15:0 data_1_i; outpu

2、t sync_o;output 15:0 data_0_o; output 15:0 data_1_o; wire n1;wire 15:0 n2; wire 15:0 n3; cf_fft_1024_8_1 s1 (clock_c, sync_i,data_0_i, data_1_i, enable_i, reset_i, n1, n2, n3);assign sync_o = n1; assign data_0_o = n2; assign data_1_o = n3;endmodulemodule cf_fft_1024_8_1 (clock_c, i1, i2, i3, i4, i5,

3、 o1, o2, o3);input clock_c; input i1;input 15:0 i2; input 15:0 i3; input i4;input i5;output o1;output 15:0 o2; output 15:0 o3; wire s1_1;wire 15:0 s1_2; wire 15:0 s1_3; wire s2_1;wire 15:0 s2_2; wire 15:0 s2_3; wire s3_1;wire 15:0 s3_2; wire 15:0 s3_3; wire s4_1;wire 15:0 s4_2; wire 15:0 s4_3; cf_ff

4、t_1024_8_23 s1 (clock_c, s3_1, s3_2, s3_3, i4, i5, s1_1, s1_2, s1_3);cf_fft_1024_8_6 s2 (clock_c, s1_1, s1_2, s1_3, i4, i5, s2_1, s2_2, s2_3);cf_fft_1024_8_5 s3 (clock_c, s4_1, s4_2, s4_3, i4, i5, s3_1, s3_2, s3_3);cf_fft_1024_8_2 s4 (clock_c, i1, i2, i3, i4, i5, s4_1, s4_2, s4_3);assign o3 = s2_3;a

5、ssign o2 = s2_2; assign o1 = s2_1; endmodule module cf_fft_1024_8_2 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input clock_c; input i1;input 15:0 i2; input 15:0 i3; input i4;input i5;output o1;output 15:0 o2; output 15:0 o3; wire 31:0 n1; wire n2;wire n3;wire 7:0 n4; wire 7:0 n5; wire 1:0 n6; wire 15

6、:0 n7; wire15:0 n8; wire 15:0 n9; wire 15:0 n10; wire 15:0 n11; wire 15:0 n12; wire s13_1; wire 31:0 s14_1; wire s15_1; wire s15_2; wire 31:0 s15_3; wire 8:0 s16_1; wire s16_2; assign n1 = i2, i3; assign n2 = s16_18; assign n3 = n2; assign n4 = s16_17,s16_16,s16_15,s16_14,s16_13,s16_12,s16_11,s16_10

7、; assign n5 = n40,n41,n42,n43,n44,n45,n46,n47; assign n6 = s15_2, s15_1;assign n7 = s15_331,s15_330,s15_329,s15_328,s15_327,s15_326,s15_325,s15_324,s15_323,s15_322,s15_321,s15_320,s15_319,s15_318,s15_317,s15_316; assign n8 = s15_315,s15_314,s15_313,s15_312,s15_311,s15_310,s15_39,s15_38,s15_37,s15_36

8、,s15_35,s15_34,s15_33,s15_32,s15_31,s15_30; assign n9 = s14_131,s14_130,s14_129,s14_128,s14_127,s14_126,s14_125,s14_124,s14_123,s14_122,s14_121,s14_120,s14_119,s14_118,s14_117,s14_116; assign n10 = s14_115,s14_114,s14_113,s14_112,s14_111,s14_110,s14_19,s14_18,s14_17,s14_16,s14_15,s14_14,s14_13,s14_1

9、2,s14_11,s14_10; assign n11 = s13_1 ? n8 : n7;assign n12 = s13_1 ? n10 : n9;cf_fft_1024_8_33 s13 (clock_c, n6, i4, i5, s13_1);cf_fft_1024_8_4 s14 (clock_c, s16_2, n1, n2, n5, i4, i5, s14_1);cf_fft_1024_8_3 s15 (clock_c, s16_2, n1, n3, n5, i4, i5, s15_1, s15_2, s15_3);cf_fft_1024_8_24 s16 (clock_c, i

10、1, i4, i5, s16_1, s16_2);assign o3 = n12; assign o2 = n11; assign o1 = s15_1; endmodule module cf_fft_1024_8_3 (clock_c, i1, i2, i3, i4, i5, i6, o1, o2, o3);input clock_c; input i1; input 31:0 i2; input i3; input 7:0 i4;input i5; input i6; output o1; output o2; output 31:0 o3; wire 7:0n1; wire 7:0 n

11、2; reg 7:0 n3; wire n4; reg n5; wire 7:0 n6; wire n7;wire n8;wire 31:0 n9; reg 7:0 n9a; reg 31:0 n9m 255:0; wire n10;wire 31:0 n11; reg 7:0 n11a; reg 31:0 n11m 255:0; reg n12;wire 31:0 n13; wire n14;wire s15_1;assign n1 = 8'b00000001; assign n2 = n3 + n1; initial n3 =8'b00000000; always (pos

12、edge clock_c)if (n14 = 1'b1)n3 <= 8'b00000000;else if (i5 = 1'b1)n3 <= n2;assign n4 = s15_1; initial n5 = 1'b0; always (posedge clock_c) if (i6 = 1'b1)n5 <= 1'b0;else if (i5 = 1'b1)n5 <= i1;assign n6 = 8'b00000000; assign n7 = n3 = n6; assign n8 = i3 &

13、 n4;initial n9a = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1) beginif (n8 = 1'b1)n9mi4 <= i2;n9a <= n3;endassign n9 = n9mn9a; assign n10 = i3 & s15_1; initial n11a =8'b00000000; always (posedge clock_c)if (i5 = 1'b1) beginif (n10 = 1'b1)n11mi4 <= i2;n11a

14、<= n3;endassign n11 = n11mn11a; initial n12 = 1'b0; always (posedgeclock_c)if (i6 = 1'b1)n12 <= 1'b0;else if (i5 = 1'b1)n12 <= n4;assign n13 = n12 ? n11 : n9; assign n14 = i1 | i6; cf_fft_1024_8_30s15 (clock_c, i1, i5, i6, s15_1);assign o3 = n13;assign o2 = n7;assign o1 = n5

15、;endmodulemodule cf_fft_1024_8_4 (clock_c, i1, i2, i3, i4, i5, i6, o1);input clock_c;input i1;input 31:0 i2; input i3;input 7:0 i4;input i5;input i6;output 31:0 o1; wire 7:0 n1;wire 7:0 n2;reg 7:0 n3;wire n4;wire n5;wire 31:0 n6; reg 7:0 n6a; reg 31:0 n6m 255:0; wire n7;wire 31:0 n8; reg 7:0 n8a; re

16、g 31:0 n8m 255:0; reg n9;wire 31:0 n10; wire n11;wire s12_1;assign n1 = 8'b00000001; assign n2 = n3 + n1; initial n3 =8'b00000000; always (posedge clock_c)if (n11 = 1'b1)n3 <= 8'b00000000;else if (i5 = 1'b1)n3 <= n2;assign n4 = s12_1; assign n5 = i3 & n4; initial n6a =

17、8'b00000000;always (posedge clock_c)if (i5 = 1'b1) beginif (n5 = 1'b1)n6mi4 <= i2;n6a <= n3;endassign n6 = n6mn6a; assign n7 = i3 & s12_1; initial n8a =8'b00000000; always (posedge clock_c)if (i5 = 1'b1) beginif (n7 = 1'b1)n8mi4 <= i2;n8a <= n3;endassign n8 =

18、n8mn8a; initial n9 = 1'b0; always (posedge clock_c)if (i6 = 1'b1)n9 <= 1'b0;else if (i5 = 1'b1)n9 <= n4;assign n10 = n9 ? n8 : n6; assign n11 = i1 | i6; cf_fft_1024_8_30s12 (clock_c, i1, i5, i6, s12_1);assign o1 = n10; endmodulemodule cf_fft_1024_8_5 (clock_c, i1, i2, i3, i4, i

19、5, o1, o2, o3);input clock_c; input i1;input 15:0 i2; input 15:0 i3; input i4;input i5;output o1;output 15:0 o2; output 15:0 o3; wire n1;wire 31:0 n2; reg n3;reg n4;reg n5;reg n6;wire 7:0 n7; reg 7:0 n8; reg 7:0 n9; reg 7:0 n10; reg 7:0n11; wire n12;reg n13;reg n14;reg n15;reg n16;wire n17;wire 1:0

20、n18; wire 15:0 n19; wire 15:0 n20; wire 15:0 n21;wire 15:0 n22; wire 15:0 n23; wire 15:0 n24; wire 15:0 s25_1;wire 15:0 s25_2; wire s26_1;wire 31:0 s27_1; wire s28_1;wire s28_2;wire 31:0 s28_3; wire 8:0 s29_1; wire s29_2;assign n1 = 1'b0; assign n2 = s25_1, s25_2; initial n3 = 1'b0;always (p

21、osedge clock_c)n3 <= 1'b0;else if (i4 = 1'b1)n3 <= s29_2; initial n4 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)n4 <= 1'b0;else if (i4 = 1'b1)n4 <= n3;initial n5 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)n5 <= 1'b0;else if (i4 = 1'b1)n5 &

22、lt;= n4;initial n6 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)n6 <= 1'b0;else if (i4 = 1'b1)n6 <= n5;assign n7 = s29_18,s29_17,s29_16,s29_15,s29_14,s29_13,s29_13,s29_11;initial n8 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n8 <= 8'b00000000;else if (

23、i4 = 1'b1)n8 <= n7;initial n9 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n9 <= 8'b00000000;else if (i4 = 1'b1)n9 <= n8;initial n10 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n10 <= 8'b00000000;else if (i4 = 1'b1)n10 <= n9;initial

24、 n11 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n11 <= 8'b00000000;else if (i4 = 1'b1)n11 <= n10;assign n12 = s29_10; initial n13 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)n13 <= 1'b0;else if (i4 = 1'b1)n13 <= n12;initial n14 = 1'b0; alwa

25、ys (posedge clock_c)if (i5 = 1'b1)n14 <= 1'b0;else if (i4 = 1'b1)n14 <= n13;initial n15 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)n15 <= 1'b0;else if (i4 = 1'b1)n15 <= n14;initial n16 = 1'b0;always (posedge clock_c)if (i5 = 1'b1)n16 <= 1'b0;

26、else if (i4 = 1'b1)n16 <= n15; assign n17 = n16; assign n18 = s28_2, s28_1;assign n19 = s28_331,s28_330,s28_329,s28_328,s28_327,s28_326,s28_325,s28_324,s28_323,s28_322,s28_321,s28_320,s28_319,s28_318,s28_317,s28_316; assign n20 = s28_315,s28_314,s28_313,s28_312,s28_311,s28_310,s28_39,s28_38,s

27、28_37,s28_36,s28_35,s28_34,s28_33,s28_32,s28_31,s28_30; assign n21 = s27_131,s27_130,s27_129,s27_128,s27_127,s27_126,s27_125,s27_124,s27_123,s27_122,s27_121,s27_120,s27_119,s27_118,s27_117,s27_116;assign n22 = s27_115,s27_114,s27_113,s27_112,s27_111,s27_110,s27_19,s27_18,s27_17,s27_16,s27_15,s27_14,

28、s27_13,s27_12,s27_11,s27_10;assign n23 = s26_1 ? n20 : n19;assign n24 = s26_1 ? n22 : n21;cf_fft_1024_8_39 s25 (clock_c, i2, i3, n1, i4, i5, s25_1, s25_2);cf_fft_1024_8_33 s26 (clock_c, n18, i4, i5, s26_1);cf_fft_1024_8_29 s27 (clock_c, n2, n6, n11, n16, i4, i5, s27_1);cf_fft_1024_8_28 s28 (clock_c,

29、 n2, n6, n11, n17, i4, i5, s28_1,s28_2, s28_3);cf_fft_1024_8_24 s29 (clock_c, i1, i4, i5, s29_1, s29_2);assign o3 = n24; assign o2 = n23; assign o1 = s28_1; endmodulemodule cf_fft_1024_8_6 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input clock_c; input i1;input 15:0 i2; input 15:0 i3; input i4;input

30、i5;output o1;output 15:0 o2; output 15:0 o3; wire s1_1;wire 15:0 s1_2; wire 15:0 s1_3; wire s2_1;wire 15:0 s2_2;wire 15:0 s2_3; wire s3_1; wire 15:0 s3_2; wire 15:0 s3_3; wire s4_1; wire 15:0 s4_2; wire 15:0 s4_3; wire s5_1; wire 15:0 s5_2; wire 15:0 s5_3; wire s6_1; wire 15:0 s6_2; wire 15:0 s6_3;

31、wire s7_1; wire 15:0 s7_2; wire 15:0 s7_3; wire s8_1; wire 15:0 s8_2; wire 15:0 s8_3; cf_fft_1024_8_21 s1 (clock_c, s2_1, s2_2, s2_3, i4, i5, s1_1, s1_2, s1_3);cf_fft_1024_8_19 s2 (clock_c, s3_1, s3_2, s3_3, i4, i5, s2_1, s2_2, s2_3);cf_fft_1024_8_17 s3 (clock_c, s4_1, s4_2, s4_3, i4, i5, s3_1, s3_2

32、, s3_3);cf_fft_1024_8_15 s4 (clock_c, s5_1, s5_2, s5_3, i4, i5, s4_1, s4_2, s4_3); cf_fft_1024_8_13 s5 (clock_c, s6_1, s6_2, s6_3, i4, i5, s5_1, s5_2, s5_3);cf_fft_1024_8_11 s6 (clock_c, s7_1, s7_2, s7_3, i4, i5, s6_1, s6_2, s6_3);cf_fft_1024_8_9 s7 (clock_c, s8_1, s8_2, s8_3, i4, i5, s7_1, s7_2, s7

33、_3);cf_fft_1024_8_7 s8 (clock_c, i1, i2, i3, i4, i5, s8_1, s8_2, s8_3);assign o3 = s1_3; assign o2 = s1_2; assign o1 = s1_1; endmodule module cf_fft_1024_8_7 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input clock_c; input i1;input 15:0 i2; input 15:0 i3; input i4;input i5;output o1;output 15:0 o2; ou

34、tput 15:0 o3; wire 1:0 n1; wire 31:0 n2;reg n3;reg n4;reg n5;reg n6;wire 7:0 n7;reg 7:0 n8; reg 7:0 n9; reg 7:0 n10; reg 7:0 n11; wire n12;reg n13;reg n14;reg n15;reg n16;wire n17;wire 1:0 n18; wire 15:0 n19; wire 15:0 n20; wire 15:0 n21;wire 15:0 n22; wire 15:0 n23; wire 15:0 n24; wire 15:0 s25_1;w

35、ire 15:0 s25_2; wire s26_1; wire s27_1; wire s27_2; wire 31:0 s27_3;wire 31:0 s28_1; wire 8:0 s29_1; wire s29_2; assign n1 = s29_18,s29_17;assign n2 = s25_1, s25_2; initial n3 = 1'b0; always (posedgeclock_c)if (i5 = 1'b1)n3 <= 1'b0;else if (i4 = 1'b1)n3 <= s29_2; initial n4 = 1

36、'b0; always (posedge clock_c)if (i5 = 1'b1)n4 <= 1'b0;else if (i4 = 1'b1)n4 <= n3; initial n5 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)n5 <= 1'b0;else if (i4 = 1'b1)n5 <= n4; initial n6 = 1'b0;always (posedge clock_c)if (i5 = 1'b1)n6 <= 1&#

37、39;b0;else if (i4 = 1'b1)n6 <= n5;assign n7 = s29_18,s29_17,s29_16,s29_15,s29_14,s29_13,s29_12,s29_11;initial n8 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n8 <= 8'b00000000;else if (i4 = 1'b1)n8 <= n7;initial n9 = 8'b00000000; always (posedge clock_c)if (i

38、5 = 1'b1)n9 <= 8'b00000000;else if (i4 = 1'b1)n9 <= n8;initial n10 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n10 <= 8'b00000000;else if (i4 = 1'b1)n10 <= n9;initial n11 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n11 <= 8'b00

39、000000;else if (i4 = 1'b1)n11 <= n10;assign n12 = s29_10; initial n13 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)n13 <= 1'b0;else if (i4 = 1'b1)n13 <= n12;initial n14 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)else if (i4 = 1'b1)n14 <= n13;initial n1

40、5 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)n15 <= 1'b0;else if (i4 = 1'b1)n15 <= n14; initial n16 = 1'b0; always (posedge clock_c)if (i5 = 1'b1)n16 <= 1'b0;else if (i4 = 1'b1)n16 <= n15; assign n17 = n16; assign n18 = s27_2, s27_1; assignn19 = s27_331

41、,s27_330,s27_329,s27_328,s27_327,s27_326,s27_325,s27_324,s27_323,s27_322,s27_321,s27_320,s27_319,s27_318,s27_317,s27_316; assign n20 = s27_315,s27_314,s27_313,s27_312,s27_311,s27_310,s27_39,s27_38,s27_37,s27_36,s27_35,s27_34,s27_33,s27_32,s27_31,s27_30;assign n21 = s28_131,s28_130,s28_129,s28_128,s2

42、8_127,s28_125,s28_124,s28_123,s28_122,s28_121,s28_120,s28_119,s28_118,s28_117,s28_116; assign n22 = s28_115,s28_114,s28_113,s28_112,s28_111,s28_110,s28_19,s28_18,s28_17,s28_16,s28_15,s28_14,s28_13,s28_12,s28_11,s28_10;assign n23 = s26_1 ? n20 : n19;assign n24 = s26_1 ? n22 : n21;cf_fft_1024_8_8 s25

43、(clock_c, i2, i3, n1, i4, i5, s25_1, s25_2);cf_fft_1024_8_33 s26 (clock_c, n18, i4, i5, s26_1);cf_fft_1024_8_28 s27 (clock_c, n2, n6, n11, n17, i4, i5, s27_1, s27_2, s27_3);cf_fft_1024_8_29 s28 (clock_c, n2, n6, n11, n16, i4, i5, s28_1);cf_fft_1024_8_24 s29 (clock_c, i1, i4, i5, s29_1, s29_2);assign

44、 o3 = n24; assign o2 = n23; assign o1 = s27_1; endmodule module cf_fft_1024_8_8 (clock_c, i1, i2, i3, i4, i5, o1, o2);input clock_c; input 15:0 i1; input 15:0 i2; input 1:0 i3;input i4;input i5;output 15:0 o1;output 15:0 o2; reg 15:0 n1; wire 7:0 n2;wire 7:0 n3; reg 15:0 n4; wire 7:0 n5; wire 7:0 n6

45、; reg 7:0 n7;reg 7:0 n8; reg 7:0 n9; reg 7:0 n10; reg 15:0 n11; wire 7:0 n12; wire 7:0 n13; wire 15:0 n14; wire 7:0 n15; reg 7:0 n16;wire 15:0 n17; wire 7:0 n18; reg 7:0 n19; wire 7:0 n20; reg 7:0 n21; wire 15:0 n22; wire 7:0 n23; reg 7:0 n24; wire 15:0 n25;wire 7:0 n26; reg 7:0 n27; wire 7:0 n28; r

46、eg 7:0 n29; wire 7:0 n30; wire 7:0 n31; wire 15:0 n32; reg 15:0 n33; wire 7:0 n34;wire 7:0 n35; wire 15:0 n36; reg 15:0 n37; initial n1 = 16'b0000000000000000;always (posedge clock_c)if (i5 = 1'b1)n1 <= 16'b0000000000000000;else if (i4 = 1'b1)n1 <= i1; assign n2 = n115,n114,n11

47、3,n112,n111,n110,n19,n18;assign n3 = n17,n16,n15,n14,n13,n12,n11,n10;initial n4 = 16'b0000000000000000;always (posedge clock_c)if (i5 = 1'b1)n4 <= 16'b0000000000000000;else if (i4 = 1'b1)n4 <= i2;assign n5 = n415,n414,n413,n412,n411,n410,n49,n48;assign n6 = n47,n46,n45,n44,n43,

48、n42,n41,n40;initial n7 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n7 <= 8'b00000000;else if (i4 = 1'b1)n7 <= n2;initial n8 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n8 <= 8'b00000000;else if (i4 = 1'b1)n8 <= n7;initial n9 = 8'b0000

49、0000; always (posedge clock_c)if (i5 = 1'b1)n9 <= 8'b00000000;else if (i4 = 1'b1)n9 <= n3;initial n10 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n10 <= 8'b00000000;else if (i4 = 1'b1)n10 <= n9;initial n11 = 16'b0000000000000000; always (posedge c

50、lock_c)if (i4 = 1'b1)case (i3)2'b00 : n11 <= 16'b0111111100000000;2'b01 : n11 <= 16'b0101101010100101;2'b10 : n11 <= 16'b0000000010000000;2'b11 : n11 <= 16'b1010010110100101;default : n11 <= 16'bxxxxxxxxxxxxxxxx;endcaseassign n12 = n1115,n1114,n

51、1113,n1112,n1111,n1110,n119,n118;assign n13 = n117,n116,n115,n114,n113,n112,n111,n110;assign n14 = 8n57, n5 * 8n127, n12;assign n15 = n1414,n1413,n1412,n1411,n1410,n149,n148,n147;initial n16 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n16 <= 8'b00000000;else if (i4 = 1'b1

52、)n16 <= n15;assign n17 = 8n67, n6 * 8n137, n13;assign n18 = n1714,n1713,n1712,n1711,n1710,n179,n178,n177;initial n19 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n19 <= 8'b00000000;else if (i4 = 1'b1)n19 <= n18;assign n20 = n16 - n19; initial n21 = 8'b00000000; a

53、lways (posedgeclock_c)if (i5 = 1'b1)n21 <= 8'b00000000;else if (i4 = 1'b1)n21 <= n20;assign n22 = 8n57, n5 * 8n137, n13;assign n23 = n2214,n2213,n2212,n2211,n2210,n229,n228,n227;initial n24 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n24 <= 8'b00000000;else

54、if (i4 = 1'b1)n24 <= n23;assign n25 = 8n67, n6 * 8n127, n12;assign n26 = n2514,n2513,n2512,n2511,n2510,n259,n258,n257;initial n27 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n27 <= 8'b00000000;else if (i4 = 1'b1)n27 <= n26;assign n28 = n24 + n27; initial n29 = 8'b00000000; always (posedge clock_c)if (i5 = 1'b1)n29 <= 8'b00000000;else if (i4 = 1'b1)n29 <= n28;assign n30 = n8 + n21; assign n31 = n10 + n29; assign n32