基于FPGA的洗衣机的设计

1、 基于FPGA的洗衣机控制电路实现姓 名： 学 号： 专 业： 2010-11-15洗衣机洗涤控制电路设计一、洗衣机洗涤控制电路的性能要求 1强洗、标准、轻柔三种洗涤模式强洗周期水流控制：正向电机接通5秒后，停2秒；再反向电机接通5秒，停2秒；然后又正向电机接通5秒。如此循环控制电机，直到洗涤定时结束。标准洗周期水流控制：其过程与强洗周期水流控制相同，不同的是正向接通时间为3.5秒，停止时间为1.5秒，反向接通时间为3.5秒。轻柔洗周期水流控制：正向接通时间为2.5秒，停止时间为1.5秒，反向接通时间为2.5秒。 2三种洗涤定时洗衣机洗涤定时可有三种选择：5分钟、10分钟、15分钟。3上电复位

2、后的初始设定初始设定为标准模式，定时时间为15分钟。如需修改可按模式选择按键和定时选择按键。每按一次按键转换一次，可多次进行循环选择。当某一次洗涤过程结束后，自动返回初始状态，等待下一次洗涤过程开始。 4启/停控制洗涤过程由启/停键控制。每按一次启/停键，状态转换一次。5洗涤定时精度洗涤定时误差要求不大于0.1秒。为简化设计洗衣机洗涤控制电路，只要求输出正向和反向的电机控制信号。二、洗衣机洗涤控制电路的结构根据上述对洗衣机洗涤控制电路的性能要求，可以画出如下图所示的结构框图。该控制器由四大部分组成：主分频器、主控制器、洗涤定时器和水流控制器。洗衣机洗涤控制电路的结构框图主分频器主分频器用来产生

3、0.1秒的时钟供主控制器使用。本方案DE2板自带时钟 ，其振荡频率为50MHz。这样，主分频器的分频系数为5M。现采用3个分频器构成主分频器的分频电路。3个分频器是1k分频器、1k分频器和5分频器。主分频器的结构如下图所示。 主分频器的结构三、洗衣机洗涤控制电路的算法状态机图描述1主控制器算法状态机图描述根据主控制器的工作要求，洗衣机洗涤时的工作状态共有以下9种：标准15分钟标准10分钟标准5分钟轻柔15分钟轻柔10分钟轻柔5分钟强洗15分钟强洗10分钟强洗5分钟 1）模式选择控制状态机图2) 定时选择控制状态机图3) 启/停控制算法状态机图描述2洗涤定时器算法状态机图描述洗涤定时器有3种状态

4、：停止状态(IDLE)、计时状态(INCCOUNT)和暂停状态(TMP_STOP)。3水流控制器算法状态机图描述该状态机图有3种状态：停止状态(STOP)、电机接通定时计数状态(ON_TIME)和电机断开定时计数状态(OFF_TIME)。四、洗衣机洗涤控制电路的VHDL语言描述1主分频器timectr_clkdiv模块主分频器的功能是将50M Hz的主频分频为10 Hz的时钟。该模块由3个进程组成，其VHDL语言描述的程序清单如下： LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY t

5、imectr_clkdiv ISPORT(sysclk:IN STD_LOGIC;clk_01:OUT STD_LOGIC);END timectr_clkdiv;ARCHITECTURE rtl OF timectr_clkdiv ISSIGNAL div1:STD_LOGIC_VECTOR(9 DOWNTO 0):="0000000000"-divide by 1k counterSIGNAL div2:STD_LOGIC_VECTOR(9 DOWNTO 0):="0000000000"-divide by 1k counterSIGNAL div3

6、:STD_LOGIC_VECTOR(2 DOWNTO 0):="000"-divide by 5 counterSIGNAL clk1,clk2:STD_LOGIC;BEGINdiv_1k:PROCESS(sysclk)BEGINIF(sysclk'EVENT AND sysclk='1')THENIF(div1="1111100111")THEN div1<="0000000000"ELSE div1<=div1+1;END IF;END IF;END PROCESS;clk1<=div1(

7、999);div_1k:PROCESS(clk1)BEGINIF(clk1'EVENT AND clk1='1')THENIF(div2="1111100111")THEN div2<="0000000000"ELSE div2<=div2+1;END IF;END IF;END PROCESS;clk2<=div2(999);div_5:PROCESS(clk2)BEGINIF(clk2'EVENT AND clk2='1')THENIF(div3="100")THE

8、N div3<="000"ELSE div3<=div3+1;END IF;END IF;END PROCESS;clk_01<=div3(2);END rtl;div_5进程为5分频进程，div_1k进程为1000分频进程。50M Hz主频经该3个进程 串行分频就得到10 Hz的时钟clk_01。 2定时器控制timer_ctr模块如前所述，定时器控制timer_ctr模块的功能是根据启/停按键(start_stop)、模式选择按键(mode_sel)和定时选择按键(time_sel)的不同输入状态，产生对应的控制信号输出，其VHDL语言描述的程序清单如

9、下。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY timer_ctr IS PORT(reset，sysclk，start_stop，mode_sel，time_sel，timer_down:IN STD_LOGIC; s5min_out，s10min_out，s15min_out，start_out:OUT STD_LOGIC; b_out，j_out，z_out:OUT STD_LOGIC);END timer_ctr; ARCHITECTURE rtl OF timer

10、_ctr IS TYPE state1TYPE IS (s_b，s_z，s_j); TYPE state2TYPE IS (s_15min，s_10min，s_5min); TYPE state3TYPE IS (s_start，s_stop); SIGNAL state1，nextstate1:state1TYPE; SIGNAL state2，nextstate2:state2TYPE; SIGNAL state3，nextstate3:state3TYPE; SIGNAL start_stop_rising，start_stop_dlayed，setstart，clrstart:STD_

11、LOGIC; SIGNAL mode_sel_dlayed，modesel_rising，time_sel_dlayed，timesel_rising， timer_down_rising:STD_LOGIC; SIGNAL set_5min，set_10min，set_15min，start，set_b，set_j，set_z， timer_down_dlayed:STD_LOGIC; BEGIN modesel_rising<=mode_sel AND (NOT mode_sel_dlayed); timesel_rising<=time_sel AND (NOT time_s

12、el_dlayed); start_stop_rising<=start_stop AND (NOT start_stop_dlayed); mode_ctr:PROCESS(modesel_rising，state1，timer_down) BEGIN set_b<='0'set_j<='0'set_z<='0' CASE state1 IS WHEN s_b => set_b<='1' IF(timer_down='1') THEN set_b<='0'

13、nextstate1<=s_b; ELSIF(modesel_rising='0') THEN nextstate1<=s_b; ELSE set_b<='0'nextstate1<=s_z; END IF; WHEN s_z => set_z<='1' IF(timer_down='1') THEN set_z<='0'nextstate1<=s_b; ELSIF(modesel_rising='0') THEN nextstate1<=s_z

14、; ELSE set_z<='0'nextstate1<=s_j; END IF; WHEN s_j => set_j<='1' IF(timer_down='1') THEN set_j<='0'nextstate1<=s_b; ELSIF(modesel_rising='0') THEN nextstate1<=s_j; ELSE set_j<='0'nextstate1<=s_b; END IF; END CASE; END PROCESS

15、;time_ctr:PROCESS(timesel_rising，state2，timer_down)BEGIN set_15min<='0' set_10min<='0'set_5min<='0' CASE state2 IS WHEN s_15min => set_15min<='1' IF(timer_down='1') THEN set_15min<='0'nextstate2<=s_15min; ELSIF(timesel_rising='

16、0') THEN nextstate2<=s_15min; ELSE nextstate2<=s_10min; END IF; WHEN s_10min => set_10min<='1' IF(timer_down='1') THEN set_10min<='0'nextstate2<=s_15min; ELSIF(timesel_rising='0') THEN nextstate2<=s_10min; ELSE nextstate2<=s_5min; END IF; W

17、HEN s_5min => set_5min<='1' IF(timer_down='1') THEN set_5min<='0'nextstate2<=s_15min; ELSIF(timesel_rising='0') THEN nextstate2<=s_5min; ELSE nextstate2<=s_15min; END IF; END CASE; END PROCESS; timer_down_rising<=timer_down AND (NOT timer_down_dla

18、yed); start_ctr:PROCESS(start_stop_rising，state3，timer_down) BEGIN setstart<='0'clrstart<='0' CASE state3 IS WHEN s_stop => IF(start_stop_rising='1') THEN nextstate3<=s_start;setstart<='1' ELSE nextstate3<=s_stop;clrstart<='1' END IF; WHEN

19、 s_start => IF(timer_down_rising='1') THEN clrstart<='1'nextstate3<=s_stop; ELSIF(start_stop_rising='1') THEN nextstate3<=s_stop;clrstart<='1' ELSE nextstate3<=s_start; END IF; END CASE; END PROCESS;time_ctr_update:PROCESS(reset，sysclk，timer_down_ris

20、ing) BEGIN IF(reset='0') THEN state1<=s_b; state2<=s_15min; state3<=s_stop;start_stop_dlayed<='0' ELSIF(sysclk'EVENT AND sysclk='1') THEN state1<=nextstate1;state2<=nextstate2;state3<=nextstate3; IF(set_b='1') THEN b_out<='1'ELSE b_

21、out<='0'END IF; IF(set_z='1') THEN z_out<='1'ELSE z_out<='0'END IF; IF(set_j='1') THEN j_out<='1'ELSE j_out<='0'END IF; IF(set_15min='1') THEN s15min_out<='1'ELSE s15min_out<='0'END IF; IF(set_10min=

22、'1') THEN s10min_out<='1'ELSE s10min_out<='0'END IF; IF(set_5min='1') THEN s5min_out<='1'ELSE s5min_out<='0'END IF; IF(timer_down_rising='1') THEN start_out<='0' ELSIF(clrstart='1') THEN start_out<='0'

23、ELSIF(setstart='1') THEN start_out<='1' END IF; mode_sel_dlayed<=mode_sel; time_sel_dlayed<=time_sel; start_stop_dlayed<=start_stop; timer_down_dlayed<=timer_down; END IF; END PROCESS;END rtl; 该模块由4个进程组成。mode_ctr进程是模式选择控制进程，对应图的模式选择控制状态机图；timer_cnt进程是定时选择控制进程，对应图的定时选择控

24、制状态机图；start_ctr进程是启/停控制进程，对应图的启/停控制算法状态机图；最后一个进程是time_ctr_update进程，它的功能是根据上述3个进程中不同的控制标志输出，在该进程中对输出控制信号进行刷新，其刷新频率为系统主时钟频率(50M Hz)，这样就可确保控制的精度。 3定时器timer_count模块定时器timer_count模块的功能是根据定时控制输出，对洗衣机的洗涤时间进行定时控制。它由3个进程构成，其VHDL语言描述的程序清单如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.

25、ALL; ENTITY timer_count IS PORT(reset，sysclk，clk_01，time_sel:IN STD_LOGIC; s5min_in，s10min_in，s15min_in，start_in:IN STD_LOGIC; timer_down_out，timer_on_out:OUT STD_LOGIC);END timer_count; ARCHITECTURE rtl OF timer_count IS COMPONENT cnt10a1 PORT(reset，clk:IN STD_LOGIC; carry:OUT STD_LOGIC); END

26、COMPONENT;COMPONENT cnt60a PORT(reset，clk:IN STD_LOGIC; ca60:OUT STD_LOGIC); END COMPONENT;TYPE stateTYPE IS (IDLE，INCOUNT，TMP_STOP); SIGNAL state，nextstate:stateTYPE; SIGNAL set_timer_on，set_timer_down，ca10，s1min，s1min_dlayed，s1min_rising，count_inc，count_clr:STD_LOGIC; SIGNAL time_sel_dlayed，time_s

27、el_rising，setdown，clrdown，seton，clron，timer_on，timer_down， timer_down_dlayed，timer_down_rising，start1，reset1，clk_01_s:STD_LOGIC; SIGNAL count，count_u:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN s1min_rising<=s1min AND (NOT s1min_dlayed); time_sel_rising<=time_sel AND (NOT time_sel_dlayed); timer_down_r

28、ising<=timer_down AND (NOT timer_down_dlayed); count_ctr:PROCESS(s1min_rising，state，start_in，count) BEGIN setdown<='0'clrdown<='0'seton<='0'clron<='0'count_inc<='0'count_clr<='0' CASE state IS WHEN IDLE =>clrdown<='1'

29、 IF(start_in='1' ANDtimer_down='0')THEN seton<='1'nextstate<=INCOUNT; ELSE clron<='1'nextstate<=IDLE;  END IF; WHEN INCOUNT =>IF(start_in='0') THEN clron<='1'nextstate<=TMP_STOP; ELSE IF(s1min_rising='1') THEN IF(count

30、/=count_u) THEN count_inc<='1'nextstate<=INCOUNT; ELSE clron<='1' setdown<='1' count_clr<='1' nextstate<=IDLE; END IF; END IF; END IF; WHEN TMP_STOP =>IF(start_in='1') THEN nextstate<=INCOUNT;seton<='1' ELSE nextstate<=TMP

31、_STOP; END IF; END CASE; END PROCESS;update:PROCESS(reset，sysclk) BEGIN IF(reset='0' AND (NOT timer_down)='0') THEN state<=IDLE;s1min_dlayed<='0'time_sel_dlayed<='0' count<="0000" ELSIF(sysclk'EVENT AND sysclk='1') THEN state<=next

32、state; IF(seton='1') THEN timer_on<='1'ELSIF(clron='1') THEN timer_on<='0'END IF; IF(clrdown='1') THEN timer_down<='0'ELSIF (setdown='1') THEN timer_down<='1'END IF; IF(count_inc='1') THEN count<=count+1; ELSIF(co

33、unt_clr='1') THEN count<="0000" END IF; s1min_dlayed<=s1min; time_sel_dlayed<=time_sel; timer_down_dlayed<=timer_down; END IF; timer_down_out<=timer_down ;timer_on_out<=timer_on; END PROCESS;INIT:PROCESS(reset，time_sel_rising，timer_down_rising) BEGIN IF(reset='

34、;0' or timer_down_rising='1') THEN count_u<="1110" ELSIF(time_sel_rising'EVENT AND time_sel_rising='1') THEN IF(s15min_in='1') THEN count_u<="1001" ELSIF(s10min_in='1') THEN count_u<="0100" ELSIF(s5min_in='1') THE

35、N count_u<="1110" END IF; END IF;END PROCESS;clk_01_s<=clk_01 AND start_in;reset1<=reset AND (NOT timer_down);u0:cnt10a1 PORT MAP(reset1，clk_01_s，ca10);u1:cnt60a PORT MAP(reset1，ca10，s1min);END rtl; count_cnt进程是定时计时进程，根据定时选择所确定的定时时间进行计时控制，它对应于图的洗涤定时算法状态机图。update进程是一个刷新进程，它根据count_

36、ctr进程的输出控制标志，对输出控制信号进行刷新。INIT进程是对本次定时器赋初值的进程。定时器根据所赋初值的时间，实现洗涤时间的控制。在timer_count清单中还含有10分频器和60分频器元件，这主要是为在本模块中得到分时钟s1min。 4水流周期控制timeronoff_ctr模块 水流周期控制timeronoff_ctr模块的功能是控制洗涤电机的通断时间，不同的洗涤模式有不同的通断时间要求。Timeronoff_ctr模块由3个进程组成，其VHDL语言描述的程序清单如下： LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LO

37、GIC_UNSIGNED.ALL; ENTITY timeronoff_ctr IS PORT(reset，sysclk，clk_01，j_in，b_in，z_in，timer_on，timer_down:IN STD_LOGIC; off_out，on_out:OUT STD_LOGIC);END timeronoff_ctr; ARCHITECTURE rtl OF timeronoff_ctr IS COMPONENT cnt5a PORT(reset，clk:IN STD_LOGIC; carry:OUT STD_LOGIC); END COMPONENT;  TY

38、PE stateTYPE IS (on_time，off_time，STOP); SIGNAL state，nextstate:stateTYPE; SIGNAL seton，clron，setoff，clroff，s05，s05_dlayed，s05_rising，reset1， cnton_inc，cnton_clr，cntoff_inc，cntoff_clr:STD_LOGIC; SIGNAL count_on，count_off，counton_u，countoff_u:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN s05_rising<=s05 AND

39、(NOT s05_dlayed); onoffcnt_ctr:PROCESS(s05_rising，state，timer_on，count_on，count_off) BEGIN seton<='0'clron<='0'setoff<='0'clroff<='0' cnton_inc<='0'cnton_clr<='0'cntoff_inc<='0'cntoff_clr<='0' CASE state IS WHEN

40、stop =>IF(timer_on='1') THEN IF(cntoff_inc='1') THEN nextstate<=off_time;setoff<='1' ELSE nextstate<=on_time;seton<='1'END IF; ELSE nextstate<=stop; END IF; WHEN on_time =>IF(timer_on='0') THEN cnton_clr<='1'nextstate<=STOP;

41、ELSE IF(s05_rising='1') THEN IF(count_on/=counton_u) THEN nextstate<=on_time;cnton_inc<='1' ELSE cnton_clr<='1' clron<='1' cntoff_inc<='1' setoff<='1' nextstate<=off_time; END IF; ELSE nextstate<=on_time; END IF; END IF; WHEN of

42、f_time =>IF(timer_on='0') THEN nextstate<=stop;clron<='1'clroff<='1' ELSE IF(s05_rising='1') THEN IF(count_off/=countoff_u) THEN nextstate<=off_time;cntoff_inc<='1' ELSE cntoff_clr<='1' clroff<='1' seton<='1'

43、cnton_inc<='1' nextstate<=on_time; END IF; ELSE nextstate<=off_time; END IF; END IF; END CASE; END PROCESS;INIT:PROCESS(j_in，b_in，z_in) BEGIN IF(j_in='1') THEN counton_u<="1010" countoff_u<="0100" ELSIF(b_in='1') THEN counton_u<="011

44、1"countoff_u<="0011" ELSIF(z_in='1') THEN counton_u<="0101"countoff_u<="0100" END IF;END PROCESS; update:PROCESS(reset1，sysclk) BEGIN IF(reset1='0') THEN state<=stop;s05_dlayed<='0'count_on<="0000" count_off<=&

45、quot;0000" ELSIF(sysclk'EVENT AND sysclk='1') THEN state<=nextstate; IF(seton='1') THEN on_out<='1'ELSIF(clron='1') THEN on_out<='0'END IF; IF(setoff='1') THEN off_out<='1'ELSIF (clroff='1') THEN off_out<='0&

46、#39;END IF; IF(cnton_inc='1') THEN count_on<=count_on+1; ELSIF(cnton_clr='1') THEN count_on<="0000" END IF; IF(cntoff_inc='1') THEN count_off<=count_off+1; ELSIF(cntoff_clr='1') THEN count_off<="0000" END IF;  s05_dlayed<=s05; E

47、ND IF; END PROCESS;reset1<=reset AND (NOT timer_down);u0:cnt5a PORT MAP(reset1，clk_01，s05);END rtl; Onoffcnt_ctr进程根据洗涤模式要求，对输出通断进行定时控制，对应图的水流控制器算法状态机图。INIT进程根据不同洗涤模式对通断进行初始化，以实现通断的定时控制。初始化的定时值以0.5秒为1个单位进行设置。最后一个进程为刷新进程update，它根据onoff_ctr进程控制标志的输出，对控制输出信号进行刷新操作。在该模块中还有一个5分频元件，它对0.1秒时钟clk_01进行分频，得到

48、0.5秒的时钟s05，作为通断定时器的计时定时脉冲。 5洗涤定时控制电路timer_sum模块洗涤定时控制电路timer_sum模块是将上述4个模块按结构化形式连接起来的整体系统模块，它实现了所提出的洗涤控制电路的功能，其VHDL语言描述的程序清单如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY timer_sum IS PORT(reset，clk，start_stop，mode_sel，time_sel:IN STD_LOGIC; p_out，m_out，on_out，of

49、f_out，start_out，timer_down_out，j_out，b_out，z_out:OUT STD_LOGIC);END timer_sum; ARCHITECTURE rtl OF timer_sum ISCOMPONENT dff3 PORT(reset，set，clk，d:IN STD_LOGIC; q，qb:OUT STD_LOGIC);END COMPONENT; COMPONENT timeronoff_ctr PORT(reset，sysclk，clk_01，j_in，b_in，z_in，timer_on，timer_down:IN STD_LOGIC; off_o

50、ut，on_out:OUT STD_LOGIC);END COMPONENT;COMPONENT timectr_clkdiv PORT( sysclk:IN STD_LOGIC; clk_01:OUT STD_LOGIC);END COMPONENT;COMPONENT timer_count PORT(reset，sysclk，clk_01，time_sel:IN STD_LOGIC; s5min_in，s10min_in，s15min_in，start_in:IN STD_LOGIC; timer_down_out，timer_on_out:OUT STD_LOGIC); END COM

51、PONENT;COMPONENT timer_ctr PORT(reset，sysclk，start_stop，mode_sel，time_sel，timer_down:IN STD_LOGIC; s5min_out，s10min_out，s15min_out，start_out:OUT STD_LOGIC; b_out，j_out，z_out:OUT STD_LOGIC);END COMPONENT;SIGNAL timer_down，s5min_s，s10min_s，s15min_s，start_s，b_s，j_s，z_s，reset1， timer_on，off_s，on_s，q_s，q

52、_b，d，set，clk_01:STD_LOGIC; BEGINset<='1'on_out<=on_s;off_out<=off_s; p_out<=q_s AND on_s AND timer_on;m_out<=q_b AND on_s AND timer_on;start_out<=start_s;timer_down_out<= timer_down;j_out<=j_s;b_out<=b_s;z_out<=z_s;u0: timer_ctr PORT MAP(reset，clk，start_sto

53、p，mode_sel，time_sel，timer_down，s5min_s，s10min_s，s15min_s，start_s，b_s，j_s，z_s);u1:timectr_clkdiv PORT MAP(clk，clk_01); u2:timer_count PORT MAP(reset，clk，clk_01，time_sel，s5min_s，s10min_s，s15min_s，start_s，timer_down，timer_on);u3:timeronoff_ctr PORT MAP(reset，clk，clk_01，j_s，b_s，z_s，timer_on，timer_down，off_s，on_s);u4: dff3 PORT MAP(reset，set，on_s，q_b，q_s，q_b);END rtl; 清单中元件u4是一个T触发器，它可实现电机正转、反转的输出控制。 6、5分频电路模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt5a IS PORT(reset,clk:IN STD_LOGIC; carry