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1、十五计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END fiveteencout;ARCHITECTURE counter OF fiveteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)
2、BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1110") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<=&quo
3、t;0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait unt
4、il (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-cloc
5、k'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL cloc
6、k = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END counter;十四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourteencout ISPORT(clk,reset,enable : IN std_logic; coun
7、t : OUT std_logic_vector(3 downto 0);END fourteencout;ARCHITECTURE counter OF fourteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count
8、_int="1101") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk=&
9、#39;1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1')
10、;- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (c
11、lock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROC
12、ESS;END counter;十三计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY thireteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END thireteencout;ARCHITECTURE counter OF thireteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGI
13、NPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1100") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN
14、-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00&q
15、uot;-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL risin
16、g_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1'
17、;);-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END counter;十二计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY twelvecout ISPORT(clk,reset,enable : I
18、N std_logic; count : OUT std_logic_vector(3 downto 0);END twelvecout;ARCHITECTURE counter OF twelvecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1'
19、 THENIF(count_int="1011") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'ev
20、ent and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock =
21、 '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '
22、;1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end
23、if;- END PROCESS;END counter;十一计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY elevencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END elevencout;ARCHITECTURE counter OF elevencout ISSIGNAL count_int:std_logic_vector(0 to 3);
24、BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1010") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001")
25、THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="
26、00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL r
27、ising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1
28、');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END counter; 十计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY count ISPORT(clk,reset,enable
29、 : IN std_logic; count : OUT std_logic_vector(3 downto 0);END count;ARCHITECTURE counter OF count ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENI
30、F(count_int="1001") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event an
31、d clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '
32、1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'
33、;-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- E
34、ND PROCESS;END counter;九计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY ninecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END ninecout;ARCHITECTURE counter OF ninecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(
35、clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1000") THENcount_int<="0000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_in
36、t<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSI
37、F-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(cl
38、ock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT
39、UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END counter;八计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY eightcout ISPORT(clk,reset,enable : IN std_logic
40、; count : OUT std_logic_vector(2 downto 0);END eightcout;ARCHITECTURE counter OF eightcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count
41、_int="111") THENcount_int<="000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk=
42、9;1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');-
43、 q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clo
44、ck'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCES
45、S;END counter;六计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY sixcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0);END sixcout;ARCHITECTURE counter OF sixcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BE
46、GINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="101") THENcount_int<="000"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="00
47、00"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (
48、clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock
49、9;event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END
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