实验三 0-9999计数器的设计

1、桂林航天工业学院学生实验报告课程名称EDA技术实验项目名称0-9999计数器的设计开课院（系）及实验室电子信息与自动化学院实验日期年月日学生姓名甘志荣学号2013090110212专业班级自动化2班指导教师庞前娟实验成绩一、实验目的1、掌握VHDL语言的基本结构及编程思想。2、掌握计数器的工作原理。3、掌握7段数码显示译码器设计。4、学习VHDL的多层次设计方法。二、实验内容1、根据计数器的原理，画出设计电路框图；2、用VHDL语言编程实现电路功能；3、下载到开发板验证；三、实验结果1、0-9999计数器的顶层设计图如下：2、0-9999计数器的低层设计（VHDL语言代码） 分频器模块f100

2、的VHDL语言代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity f100 is generic(n1 :integer:=50000000); port(clk:in std_logic; f1:out std_logic);end entity f100;architecture getsec of f100 is -signal secout1 : std_logic :='1' signal cnt1: integer range 0 to n1-1:=0;

3、beginprocess(clk) isbeginif clk'event and clk='1' then cnt1<=cnt1+1; if cnt1<=n1/2 then f1<='0' else f1<='1' end if; if cnt1>=n1-1 then cnt1<=0; end if;end if;end process;end architecture getsec; 计数器模块cout的VHDL语言程序代码：library ieee;use ieee.std_logic_1164.

4、all;use ieee.std_logic_unsigned.all;entity cout isport(clk:in std_logic; cn1,cn2,cn3,cn4:out std_logic_vector(3 downto 0);end ;architecture c10 of cout is signal temp1,temp2,temp3,temp4:std_logic_vector(3 downto 0); signal g,s,b:std_logic;begin p1:process(clk) begin if( clk'event and clk='1&

5、#39; )then if temp1<"1001"then temp1<=temp1+1;g<='0' else temp1<="0000"g<='1' end if; end if; end process p1; p2:process(g) begin if( g'event and g='1' )then if temp2<"1001"then temp2<=temp2+1;s<='0' else temp2

6、<="0000"s<='1' end if; end if; end process p2; p3:process(s) begin if( s'event and s='1' )then if temp3<"1001"then temp3<=temp3+1;b<='0' else temp3<="0000"b<='1' end if; end if; end process p3; p4:process(b) begin

7、 if( b'event and b='1' )then if temp4<"1001"then temp4<=temp4+1; else temp4<="0000" end if; end if; end process p4; cn1<=temp1;cn2<=temp2;cn3<=temp3;cn4<=temp4;end; 显示模块display的VHDL语言的程序代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logi

8、c_unsigned.all;-use ieee.numeric_std.all;-use ieee.std_logic_signed.all;entity display isport(data1,data2,data3,data4:in std_logic_vector(3 downto 0); clk_s:in std_logic; -reset:in std_logic; wei:out std_logic_vector(3 downto 0); duanxuan:out std_logic_vector(7 downto 0);end ;architecture aa of disp

9、lay is signal b:std_logic_vector(1 downto 0); signal temp:std_logic_vector(3 downto 0); signal duan:std_logic_vector(7 downto 0);begin a1:process(clk_s) begin if clk_s'event and clk_s='1' then b<=b+1; end if; end process a1; a2:process(b) begin case b is when "00"=>wei<

10、;="1110" temp<=data1; when "01"=>wei<="1101" temp<=data2; when "10"=>wei<="1011" temp<=data3; when "11"=>wei<="0111" temp<=data4; end case; end process a2; a3:process(temp) begin case temp is when&quo

11、t;0000"=>duan<="11000000" when"0001"=>duan<="11111001" when"0010"=>duan<="10100100" when"0011"=>duan<="10110000" when"0100"=>duan<="10011001" when"0101"=>duan<

12、="10010010" when"0110"=>duan<="10000010" when"0111"=>duan<="11111000" when"1000"=>duan<="10000000" when"1001"=>duan<="10010000" when others=>duan<="11111111" end case; end process a3; duanxuan<=duan;end; 四、实验结果分析 本次实验用了两个分频器，一个用于计数分出1HZ，一个用于数码管的动态显示分出25000HZ。在计数模块的CLK接入分频器分出的1HZ,也就是来一个上升沿