教案成果讲稿

1、Terasic TechnologiesCompany IntroductionOutlineOutlinen DE1-SoC快速入门n SoC FPGA设计流程n DE1-SoC硬件实验n DE1-SoC软件实验n DE1-SoC进阶应用DemoDE1SoC快速入门开发设计软件n Altera Quartusn Altera SoC Embedded Design Suite实验文件目录内容cdDE1-SoC开发板光盘.内有原理图,设计范例等lab本次实验课所使用到的设计范例tool实验中所需要的驱动,软件工具(Quartus, EDS.etc.).DE1SoC Mode Select Sw

2、itchMSEL4:0设定模式描述10010ASFPGA configured from EPCQ (default)01010FPPx32FPGA configured from HPS software: Linux00000FPPx16FPGA configured from HPS software: U-Boot, with image stored on the SD card, like LXDE Desktop or console Linux with frame buffer edition.DE1SoC连接设定n USB Blaster IIn UART-to-USBn

3、Power Jack安装USB Blaster II驱动n USB Blaster II :FPGA code, Debug HPS / FPGA.sof入FPGA测试安装UARTtoUSB驱动设定串口终端工具n Speed : 115200n Serial Line :COMxn Connection : Serial在DE1SoC上运行Linuxn 将MicroSD cardDE1-SoCSoC FPGA设计流程SoC FPGA系统开发流程SoC FPGA系统架构n 处理器 4000 MIPs (up to 800Mhz per core) 双核ARM Cortex-A9处理器处理引擎 N

4、EON 丰富的内嵌设备 32-KB L1 Caches每核 512-KB L2 Cachen 硬核内存器 支持DDR2, DDR3和LPDDR2 支持ECCn 高带宽通道 HPS to FPGA FPGA to HPS FPGA to HPS SDRAMHPS IP Featuresn 双核ARM Cortx-A9处理器器n SDRAMn DMA器n 2 Ethernet MACsn NAND, QSPI, SD和器MMC flashn Serial Interface器- 2 USB OTG- 2 SPI master- 2 SPI slave器器器器- 4 I2C- 2 CANn 2串口n

5、 GPIOSoC FPGA 设计理念n FPGA: 看起来像FPGA 用起来像FPGA 标准的FPGA开发流程 使用传统的开发工具: Qurtus II, Qsys, Signal TabII ,System Console , ProgrammerARM HPS: 看起来像ARM处理器系统 用起来像ARM处理器系统 传统的ARM处理器开发流程 使用传统的ARM处理器开发工具:nARM Cortex-A9 cor/debuer JTAG toolsro ram traceSoC硬件设计流程创建Quartus IIQsys系统集成工具n 使用GUI接口来做系统设计n 简化系统开发的复杂性n 为I

6、P模块间自动生成内部连接提供标准开发平台IP integrationCustom IP authoring IP verificationn设计可再利用n为Qsys系统增添组件n 包括HPS,现有的IP和客制化IP组件都可以在Qsys的component Library 呼叫使用n 可使用搜寻功能来找寻IPn 鼠标点击IP组件便可加入系统创建一个新的Qsys系统HPS组件设定HPS组件设定页面n FPGA Interfacesn Peripheral MultiplexingHPClocksn SDRAMAdd Custom Components to Qsysn 使用Component Ed

7、itorn 支持标准Interfaces Avalon-MM (memory mapped) Avalon-ST (streaming) ARM AXI 3.0 & 4.0 ARM APB ARM AHB建立元件間的連線n 透过鼠标左键点击拉线建立连结n 透过鼠标右键选择特定接口来建立连接Generate Completed SystemSystem Consolen Quick system-level debug of Qsys systems Interactive Tcl Console Debug over various communication channels JTAG, U

8、SB or TCP/IP Read form or write to memory mapped components No processor requiredOn Chip Component DebugSoC硬件实验硬件实验流程 了解DE1-SoC硬件系统架构 检视HPS系统 添加并配置LED和Button PIO组件 编译生成Qsys系统 编辑并编译Quartus II工程 验证硬件系统设计DE1SoC系统框图定义硬件系统架构Golden Hardware Reference Design (GHRD)n 提供DE1-SoC 完整的Quartus II 專案 基本的頂層top.v 文件

9、 Qsys : HPS (pin mux / ddr3 / clocketc.) , AXI-bridge, On-ChipRAM and basic FPGA component完整的 Pin assignment , SDC文檔n 可在 DE1-SoC CD內取得GHRD Qsys组件一览n Golden System Reference Design配置HPS系统(1)配置HPS系统(2)HPS组件设定通用选项与Bootn Events Event in and outt for event condition Wait for interrupt conditionn GIPOn De

10、bug interfacen Boot from FPGAFPGAHPS InterfacesHSP FPGA AXI BridgeAXI Bridgesn FPGA-to-HPS外设与内存 4GB space Widths 32, 64, 128n HPS-to-FPGA 960 MB space Widths 32, 64, 128n Lightweight HPS-to-FPGA Low performance (32 bits) 可以对FPGA组件 2 MB space并状态n 可以连接Avalon总线FPGAtoSDRAMFPGAtoHPS SDRAM Interfacesn AXI

11、-3 or Avanlon-MMn Select the number of interfacesn Data widths: 32, 64, 128, 256Other Interfaces to the HPSn Resets FPGA can control debug, warm or cold reset signals HPS can send cold and warm reset signals to FPGAn DMA requests Enable up to 8 from the FPGAn Interrupts 64 inputs from FPGA to HPS in

12、terrupt controller HPS peripheral interrupt output to FPGAHPS I/O Muxing OverviewPeripheral Pin Multiplexingn Enable peripheral interface and choose modesn Select I/O setHPS I/O管脚特性n 可使用的外设的数目多于HPS I/Osn 多数外设需要共享HPS I/OsPin Usage andsHPS Pin Assignmentsn HPS管脚设定会自定被Quartus compiler设定n SDRAM I/O需要执行.

13、tcl来设定 执行hps_sdram_po_pin_assigments.tclI/O StandardHPS Clock Block DiagramHPS Clockn Enable HPS clocks into the FPGAn Drive FPGA clocks into HPS PLLs Peripherals SDRAMSDRAMn 一至的SDRAM GUI Megafunction界面n 支持数种内存 DDR3 DDR2 LPDDR2n 设置clock以及初始设定設定SDRAM 的 Timing & SkewSoC EDS ContentsSoC Embedded Develo

14、pment Suite (SoCn Contains everything you need for firmware and application development on the Altera SoC hardware platform Board bring up Bare-mapplication development and debugging Device driver development Linux based application development and debugging Debug systems running symmetrical multipr

15、ocessing Debug software targeting sthat resides in the FfabricEDS ConntsComponentKey FeatureWeb EditionSubscription EditionEclipse IDEARM Development Studio 5(DS5) Altera Edition ToolkitDebugging over Ethernet (Linux)Debugging over USBBlaster II (JTAG)Automatic register viewsHardware crosstriggering

16、CPU/FPGA event correlationHardware/Software Interface ToolsPreloader Support Package GeneratorDevice Tree GeneratorCompiler ToolsLinaro Linux GCC tool chain (armlinux gnueabihf)Mentor CodeBench Lite BaremGCCtool chain(armnoneeabi)SoC Hardware LibrariesHWLibsSoC Programming ExamplesGolden Hardware Re

17、ference Design,Variety of software and Linux examplesARM DS5 Altera EditionSelectPerspectiveOutline ViewFile ViewerProjectTerminalWindowEmbedded Command ShellnCygwin base build environmentnSimilar to Nios Command ShellnembeddedEmbedded_Comannd_Sheel.batHard Ware to Software Handoff FilesGenerated Ha

18、ndoff Filesn Handoff for the preloader generator Contains information chosen during HPS component instantiation Preloader generator uses hand off to generate the preloader binary which used to setup the pin mux, SDRAM, clocks, etc.n System View Description file (CMSIS-SVD) XML file allows registers

19、of soft IP in FPGA to show within the DS-5n .sopcinfo Describes the FPGA system to Alteras device tree generator for uses in the linux envionment生成PreloaderApplication Class Processor Booting FlowBootROMStored in onchip ROMPreloaderStored in flash, runs from SDRAMUBootStored in flash, runs from SDRA

20、MSDRAMRunApplication生成Preloader 流程Handoff FolderHandoff FolderPreloader SourcePreloaderImageFileDescriptionuboot-socfpga/spl/u-boot-splPreloader ELF fileuboot-socfpga/spl/u-boot-spl.binPreloader binary file生成Device TreeLinux Device Tree生成Device Tree流程SOPC Info File.dts文件内容生成Device Tree Flow可Boot Linux MicroSD Card内容ARM DS5 Altera EdtionARM DS5 AlterEdtionn File editingn Project managementn Debugging Run control (Run, stop , breakpoints) Variables/Watch view HPS Register View FPGA and Soft IP Register Tracing Cross-Triggering Profiling(using CMSIS-SVD fil