数字系统设计补充讲义数电cmos

1、Digital CircuitsLect补充-CMOS Gate刘 鹏浙江大学信息与电子工程学系liupeng May. 22, 2012MOS管结构和符号MVistorV之当结所以D-S间不导通. iD=0门电路 (2)FALL 2008ZDMCVDDVGS(th)N+|VGS(th)P|，CMOS 反相器VGS(th)N-NMOS的开启电压VGS(th)P-PMOS的开启电压VGS(th)N=|VGS(th)P|工作原理：1、输入为低电平VVGS1VGS(th)N=0V时ILT1管截止；T2导通PMOS|VGS2| |VGS(th)P|电路中电流近似为零（忽略T1的截衬止底漏与电漏流源）间

2、,V的P主N结要始降终落处在于T反漏极相连做输出端NMOS偏，NMOS管的衬DD底总是接到电1路上，输出为高电平VOHVDD的最低电位，PMOS管的衬底总是2、输入为高电平VIH = VDD时，接到电路的最高电位T1 通T2 止，VDD主要降在T2 上，柵极相连做输入端输出为低电平V 0V。OL实现逻辑“非”功能F = A门电路 (3)FALL 2008ZDMC与非门逻辑两个并联的MOS门电路PMOS管T3、T4止二输入“与非”门电路结构如图通 1 当A和B为高电:输出低电平当A和B有一个或一个以上 0 止为低电电路输出: 1 通电路F两NMOS联的T1、T2门电路 (8)MC每个输入端与一

3、个实NMOS管和一个PMOS 管的栅极相连或非门逻辑功能的CMOS门电路两个串联的PMOS管01VDD二输入“或非”门电T1、T3止通T3当A和B为低电:00A输出高电平通T1当A和B有一个或一个以上为01 Y高电:T4通T2电路输出低电平电路实现“或非”逻辑功能F = A + B止止两个并联的NMOST1、T2门电路 (9)FALL 2008ZDMCTransistor-level Logic Circuits (inv)Vdd(NOT gate):Gndwhat is the relationship between in and out?Vddinout0 volts3 voltsGnd

4、门电路 (11)FALL 2008ZDMCLogical Values+3+3Logic 1Logic 0Input VoltageLogic 1Input VoltageVVoutLogic 000+5VinThresholdn Logical 1 (true) : V > Vdd V thn Logical 0 (false) : V < VthNoise margin?nnot( out, in)n门电路 (12)FALL 2008ZDMCinoutF TTFComputing with Switchesn Compose switches into more complex

5、 functions:(Boolean)BAANDZ º A and BAORZ º A or BBTwo fundamental structures: series (AND) and parallel (OR)门电路 (13)FALL 2008ZDMCTransistor-level Logic Circuits - NANDNAND gatenn Inverter (NOT gate):nand (out, a, b)aboutLogic Function:n001101011110out = 0 iff both a AND b = 1 therefore out

6、 = (ab)pFET network and nFET network are duals of one another.nnHow about AND gate?门电路 (14)FALL 2008ZDMCTransistor-level Logic CircuitsSimple rule for wiring up MOSFETs:nFET is used only to pass logic zero.pFet is used only to pass logic one. For example, NAND gate:nnnNote: This rule is sometimes vi

7、olatedby expert designers under special conditions.门电路(15)FALL 2008ZDMCTransistor-level Logic Circuits - NORNOR gatenNAND gatenFunction:nout = 0 iff both a OR b = 1 thereforeout = (a+b)Again pFET network and nFET network are duals of one another.Other more complex functions are possible. Ex: out = (

8、a+bc)aboutnnor (out, a, b)001101011000nn门电路 (16)FALL 2008ZDMCTransmission GateTransmission gates are the way to build “switches” in CMOS.Both transistor types are needed:n nFET to pass zeros.nnn pFET to pass ones.The transmission gate is bi-directional (unlike logic gatesnand tri-state buffers).Func

9、tionally it is similar to the tri-state buffer, but does not connect to Vdd and GND, so must be combined with logicngates or buffers.门电路 (20)FALL 2008ZDMCCMOS三态门1.电路组成VDDENT'13.原理：EN = 0,T '1 T '2 导通,Y = A Y AEN = 1,T '1 T '2 截止，Y为高阻态4.三态门的应用主要应用： 总线逻辑 双向传输T'212.逻辑符号AYEN门电路 (

10、21)FALL 2008ZDMCT1T2Transistor-level Logic CircuitsTri-state BuffernTransistor circuit for inverting tri-state buffer:n“high impedance”(output disconnected)n VariationsInverting bufferInverted enable“transmission gate”Tri-state buffers are used when multiple circuits all connect to a common bus. Onl

11、y one circuit at a time is allowed to drive the bus. All others “disconnect”.门电路 (22)FALL 2008ZDMCTransistor-level Logic Circuits - MUXMultiplexorTransistor Circuit for inverting multiplexor:nnIf s=1 then c=b门电路 (23)FALL 2008ZDMCa else c=Unused InputsCMOS inputs should be never be left disconnected.

12、 All CMOS inputs must be tied either to a fixed voltage level (0V or VDD) or to another input.This rule applies even to the inputs of extra unused logic gates on a chip.An unconnected CMOS input is susceptible to noise and static charges that could easily bias both the P- channel and the N-channel MOSFETs in the conductive state, resulting in increased power dissipation and possible overheating.nnn门电路 (24)FALL 2008ZDMCCMOS电路的特点功耗小：CMOS门工作时，总是一管导通另一管截止，