FPGA ADTLC实验

1、/*程序名称： AD_TLC549实验*主要功能： 将测量的电压值显示在LCD1602上*说 明：*作 者： JZHG*时 间： 2012-05-12*版 本： JZHG-V2.3 */ module Top_Module ( clk, rst_n, AD_DO, AD_CS, AD_CLK, RS, EN, DO ); /- / Define PORT input clk; / Clock input rst_n; / Reset input AD_DO; output AD_CS; output AD_CLK; output RS; output EN; output 7:0 DO; /-

2、/ TLC549 Module wire 7:0 AD_data; TLC549_Module U1(.clk( clk ),.rst_n( rst_n ),.AD_DO( AD_DO ),.AD_CS( AD_CS ),.AD_CLK( AD_CLK ),.AD_data( AD_data ) );/-/ Data Dispose Modulewire 23:0 data_out;Data_Dispose_Module U2( .clk( clk ), .rst_n( rst_n ), .data_in( AD_data ), .data_out( data_out ) );/-/ LCD1

3、602 ModuleLCD1602_Module U3( .clk( clk ),.rst_n( rst_n ),.LCD_data( data_out),.RS( RS ),.EN( EN ),.DO( DO );/-endmodule/* * TLC549 Module * */ module TLC549_Module (clk,rst_n,AD_DO,AD_CS,AD_CLK,AD_data ); /- / Define PORT input clk; / Clock input rst_n; / Reset input AD_DO; output AD_CS; output AD_C

4、LK; output 7:0 AD_data; /- / SET AD CLock reg 5:0 cnt; reg clk_1; always ( posedge clk or negedge rst_n )if ( !rst_n ) begin cnt = 6d0; clk_1 = 1b0;endelse if ( cnt = 6d50 ) cnt = cnt + 1b1; / T = 2uselse begin cnt = 6d0;clk_1 = clk_1;end/-/ Delay reg 4:0 T; always ( negedge clk_1 or negedge rst_n )

5、if ( !rst_n ) T = 5d0;else T = T + 1b1; /- / Read Data reg CS_r; reg CLK_r; reg 7:0 data_r; reg 7:0 BUF; always ( posedge clk_1 or negedge rst_n ) if ( !rst_n ) begin CS_r = 1b1; CLK_r = 1b0; data_r = 8d0; BUF = 8d0; end else case ( T ) 0, 1: begin CS_r = 1b0; CLK_r = 1b0; end 2, 3, 4, 5, 6, 7, 8, 9

6、: begin CLK_r = 1b1; data_r0 = AD_DO; data_r 7:1 = data_r 6:0 ; end default: begin CS_r = 1b1; CLK_r = 1b0; BUF = data_r; end endcase /- assign AD_CS = CS_r; assign AD_CLK = CLK_r ? clk_1 : 1b0; assign AD_data = BUF; /- Endmodule/* * Data dispose Module * */ module Data_Dispose_Module ( clk, rst_n,

7、data_in, data_out );/-/Define PORT input clk; input rst_n; input 7:0 data_in; output 23:0 data_out; /- / Data * 100 reg 31:0 temp; always ( posedge clk or negedge rst_n )if ( !rst_n ) temp = 8d0; else temp = data_in * 100/( 95 ); /- / Data Dispose reg 31:0 bai; reg 31:0 shi; reg 31:0 ge; always ( po

8、sedge clk or negedge rst_n )if ( !rst_n ) begin bai = 32d0;shi = 32d0;ge = 32d0;endelse begin bai = temp / 100 + 0; shi = temp % 100 /10 + 0; ge = temp % 10 + 0;end /- assign data_out = bai 7:0 , shi 7:0 , ge 7:0 ; /- endmodule /* * LCD1602 Module * */ module LCD1602_Module ( clk,rst_n,LCD_data,RS,E

9、N,DO);/-/ Define PORTinput clk; / Clockinput rst_n; / Resetinput 23:0 LCD_data;output RS;output EN;output 7:0 DO;/-/ Set LCD1602 Clockreg 15:0 cnt;reg LCD_clk;always ( posedge clk or negedge rst_n )if ( !rst_n ) begin cnt = 16d0; LCD_clk = 1b0; endelse if ( cnt = 16d50_000 ) cnt = cnt + 1b1; / T = 2

10、mselse begin cnt = 16d0; LCD_clk = LCD_clk;end/-reg 3:0 i;reg RS_r;reg EN_r;reg 7:0 DO_r;always ( posedge LCD_clk or negedge rst_n )if ( !rst_n ) begin i = 4d0;RS_r = 1b0;EN_r = 1b0;DO_r = 8d0;endelse case ( i )/=/ Init LCD 0: begin EN_r = 1b1; RS_r = 1b0; DO_r = 8h38; i = i + 1b1; end 1: begin RS_r

11、 = 1b0; DO_r = 8h08; i = i + 1b1; end 2: begin RS_r = 1b0; DO_r = 8h01; i = i + 1b1; end 3: begin RS_r = 1b0; DO_r = 8h06; i = i + 1b1; end 4: begin RS_r = 1b0; DO_r = 8h0C; i = i + 1b1; end /= / Write DATA 5: begin RS_r = 1b0; DO_r = 8h80; i = i + 1b1; end / write addr 6: begin RS_r = 1b1; DO_r = L

12、CD_data 23:16 ; i = i + 1b1; end / write data 7: begin RS_r = 1b0; DO_r = 8h81; i = i + 1b1; end / write addr 8: begin RS_r = 1b1; DO_r = .; i = i + 1b1; end / write data 9: begin RS_r = 1b0; DO_r = 8h82; i = i + 1b1; end / write addr 10: begin RS_r = 1b1; DO_r = LCD_data 15:8 ; i = i + 1b1; end / write data 11: begin RS_r = 1b0; DO_r = 8h83; i = i + 1b1; end / write addr 12: begin RS_r = 1b1; DO_r = LCD_data 7:0 ; i = i + 1b1; end / write data 13: begin RS_r