基于verilog语言简易电子琴设计数字电子技术课程设计报告

1、数字电子技术课程设计报告基于verilog HDL语言的简易电子琴设计 学 院：_信息与控制工程学院_ 专业班级：_电气11级四班_ 姓 名：_商玉玺_ 学 号：_11053421_ 指导教师：_一、实验目的 1、学习verilogHDL语言的基本运用，能够利用其进行简单编程； 2、学习使用Quartus 7.0的基本操作，能够利用其进行简单的设计； 3、结合实践加深对理论知识的理解。二、设计题目 用verilogHDl语言设计简易电子琴。三、题目要求 （1）单独从左至右按下S1-S7每个按键后能够各自对应发出 “哆来咪发唆啦西”的音乐声；（2）按下最右边按键（S8），同时再配合按下S1-S7

2、键后，发高八度的对应音；（3）按键需要进行“消抖”处理；（4）外部输入脉冲信号频率为1mhz；（5）扩展要求：自主设计（增加低8度功能，自动播放一段音乐)。四、设计原理（1）喇叭的振动频率不同，导致产生不同的声音；振动频率越低，声音越低沉，振动频率越高，声音越尖锐。题目中音乐基本音的 “哆”对应频率为523Hz 、“来”对应频率为587Hz 、“咪”对应频率为659Hz 、“发”对应频率为698Hz 、“唆”对应频率为784Hz 、“啦”对应频率为880Hz 、“西”对应频率为998Hz。低8度音：基本音频率/2，例如低音1的频率为523/2=261.5Hz。高8度音：基本音频率×2

3、，例如高音1的频率为523×2=1046Hz.。不同的频率产生利用给定的时钟脉冲来进行分频实现。（2）消抖的原理：按键默认输入逻辑1，当有按键按下时对应的输入为逻辑0（但会存在抖动），当FPGA开始检测到该引脚从1变为0后开始定时（按键抖动时间大约10ms），定时时间结束后若该引脚仍然为0则表示确实发生按键按下，否则视为抖动而不予以理会；按键松开过程的消抖处理和按下时原理一样。（3）原理框图四、管脚对应表信号名称对应FPGA管脚名说明1MHzL2基准时钟OUF3音频输出S1F8基本功能按键S2A14S3F10S4B16S5F12S6B17S7F15S8B18BT1M1扩展功能按键BT

4、2M2BT3U12BT4U11五、实验过程1、设计按键防抖模块（1）设计程序module xiaodou(rst,clk_1M,out);input clk_1M;input rst;output out;wire rst;reg out;reg24:0cnt;reg2:0state;parameter state0=3'b000, state1=3'b001, state2=3'b010, state3=3'b011, state4=3'b100, state5=3'b101;always(posedge clk_1M)begincnt<

5、=24'd0;case(state) state0:if(!rst)beginout=0;state<=state1;end elsestate<=state0; state1:beginout=0;cnt<=cnt+1;if(cnt=10000)state<=state2;elsebegin/out=1;state<=state1;endend state2:if(!rst)state<=state3;elsestate<=state0; state3:if(!rst)begin out=1;cnt<=0;/state<=stat

6、e3;end elsestate<=state4; state4:begincnt<=cnt+1;if(cnt=200000)beginout=1;state<=state5;endelsebeginout=1;state<=state4;endend state5:if(rst)beginout=0;state<=state0;end else state<=state3;endcaseendendmodule（2）原理图及仿真波形2、按键识别模块设计（1）程序设计module xkey(a,b,c,d,e,f,g,h,l,qout);input a,b,

7、c,d,e,f,g,h,l;output qout;reg 8:0 qin;reg 4:0 qout;always(a or b or c or d or e or f or g or h or l)begin qin8=a; qin7=b; qin6=c; qin5=d; qin4=e; qin3=f; qin2=g; qin1=h; qin0=l;endalways(qin)begincase(qin)9'b100000000:qout<=5'b00001;9'b010000000:qout<=5'b00010;9'b001000000:

8、qout<=5'b00011;9'b000100000:qout<=5'b00100;9'b000010000:qout<=5'b00101;9'b000001000:qout<=5'b00110;9'b000000100:qout<=5'b00111;9'b100000010:qout<=5'b01000;9'b010000010:qout<=5'b01001;9'b001000010:qout<=5'b01010;9'

9、;b000100010:qout<=5'b01011;9'b000010010:qout<=5'b01100;9'b000001010:qout<=5'b01101;9'b000000110:qout<=5'b01110;9'b100000001:qout<=5'b01111;9'b010000001:qout<=5'b10000;9'b001000001:qout<=5'b10001;9'b000100001:qout<=5'

10、b10010;9'b000010001:qout<=5'b10011;9'b000001001:qout<=5'b10100;9'b000000101:qout<=5'b10101;9'b000000000:qout<=5'b00000;9'b000000010:qout<=5'b00000;9'b000000001:qout<=5'b00000;default:qout<=0;endcaseendendmodule（2）原理图及仿真波形3、分频器模块的设计

11、（1）程序设计module fenpin(in,clk_1M,out);input in;input clk_1M;output out;wire4:0in;reg out;reg11:0count;reg4:0state;initialcount<=12'd0;parameter state0=5'b00000, state1=5'b00001, state2=5'b00010, state3=5'b00011, state4=5'b00100, state5=5'b00101, state6=5'b00110, stat

12、e7=5'b00111, state8=5'b01000, state9=5'b01001, state10=5'b01010, state11=5'b01011, state12=5'b01100, state13=5'b01101, state14=5'b01110, state15=5'b01111, state16=5'b10000, state17=5'b10001, state18=5'b10010, state19=5'b10011, state20=5'b10100,

13、 state21=5'b10101, state22=5'b10110;always(posedge clk_1M)begincase(state)state0:begin/if(allin=5'b10110)/state<=state0;if(in=5'b00001)state<=state1;else if(in=5'b00010)state<=state2;else if(in=5'b00011)state<=state3;else if(in=5'b00100)state<=state4;else i

14、f(in=5'b00101)state<=state5;else if(in=5'b00110)state<=state6;else if(in=5'b00111)state<=state7;else if(in=5'b01000)state<=state8;else if(in=5'b01001)state<=state9;else if(in=5'b01010)state<=state10;else if(in=5'b01011)state<=state11;else if(in=5'

15、b01100)state<=state12;else if(in=5'b01101)state<=state13;else if(in=5'b01110)state<=state14;else if(in=5'b01111)state<=state15;else if(in=5'b10000)state<=state16;else if(in=5'b10001)state<=state17;else if(in=5'b10010)state<=state18;else if(in=5'b10011

16、)state<=state19;else if(in=5'b10100)state<=state20;else if(in=5'b10101)state<=state21;else if(in=5'b00000)state<=state22;elsestate<=state0;endstate1:beginif(count<=956)beginbegincount=count+12'd1;endif(in=5'b00001)state<=state1;elsebeginout=0;state<=state0

17、;endendelsebeginbeginout=out;count=0;endif(in=5'b00001)state<=state1;elsebeginout=0;state<=state0;endendendstate2:begin if(count<=852)begin begin count=count+12'd1;end if(in=5'b00010)state<=state2;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end i

18、f(in=5'b00010)state<=state2;else begin out=0;state<=state0;end end endstate3:begin if(count<=759)begin begin count=count+12'd1;end if(in=5'b00011)state<=state3;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b00011)state<=state3;el

19、se begin out=0;state<=state0;end end endstate4:begin if(count<=716)begin begin count=count+12'd1;end if(in=5'b00100)state<=state4;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b00100)state<=state4;else begin out=0;state<=state0;end e

20、nd endstate5:begin if(count<=638)begin begin count=count+12'd1;end if(in=5'b00101)state<=state5;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b00101)state<=state5;else begin out=0;state<=state0;end end endstate6:begin if(count<=568)b

21、egin begin count=count+12'd1;end if(in=5'b00110)state<=state6;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b00110)state<=state6;else begin out=0;state<=state0;end end endstate7:begin if(count<=501)begin begin count=count+12'd1;end

22、if(in=5'b00111)state<=state7;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b00111)state<=state7;else begin out=0;state<=state0;end end endstate8:begin if(count<=478)begin begin count=count+12'd1;end if(in=5'b01000)state<=state8;e

23、lse begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b01000)state<=state8;else begin out=0;state<=state0;end end endstate9:begin if(count<=426)begin begin count=count+12'd1;end if(in=5'b01001)state<=state9;else begin out=0;state<=state0;end

24、endelse begin begin out=out;count=0;end if(in=5'b01001)state<=state9;else begin out=0;state<=state0;end end endstate10:begin if(count<=380)begin begin count=count+12'd1;end if(in=5'b01010)state<=state10;else begin out=0;state<=state0;end endelse begin begin out=out;count=0

25、;end if(in=5'b01010)state<=state10;else begin out=0;state<=state0;end end endstate11:begin if(count<=358)begin begin count=count+12'd1;end if(in=5'b01011)state<=state11;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b01011)state<=

26、state11;else begin out=0;state<=state0;end end endstate12:begin if(count<=319)begin begin count=count+12'd1;end if(in=5'b01100)state<=state12;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b01100)state<=state12;else begin out=0;state<

27、=state0;end end endstate13:begin if(count<=284)begin begin count=count+12'd1;end if(in=5'b01101)state<=state13;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b01101)state<=state13;else begin out=0;state<=state0;end end endstate14:begin i

28、f(count<=251)begin begin count=count+12'd1;end if(in=5'b01110)state<=state14;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b01110)state<=state14;else begin out=0;state<=state0;end end endstate15:begin if(count<=1912)begin begin count

29、=count+12'd1;end if(in=5'b01111)state<=state15;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b01111)state<=state15;else begin out=0;state<=state0;end end endstate16:begin if(count<=1704)begin begin count=count+12'd1;end if(in=5'

30、b10000)state<=state16;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b10000)state<=state16;else begin out=0;state<=state0;end end endstate17:begin if(count<=1518)begin begin count=count+12'd1;end if(in=5'b10001)state<=state17;else beg

31、in out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b10001)state<=state17;else begin out=0;state<=state0;end end endstate18:begin if(count<=1432)begin begin count=count+12'd1;end if(in=5'b10010)state<=state18;else begin out=0;state<=state0;end end

32、else begin begin out=out;count=0;end if(in=5'b10010)state<=state18;else begin out=0;state<=state0;end end endstate19:begin if(count<=1276)begin begin count=count+12'd1;end if(in=5'b10011)state<=state19;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;

33、end if(in=5'b10011)state<=state19;else begin out=0;state<=state0;end end endstate20:begin if(count<=1136)begin begin count=count+12'd1;end if(in=5'b10100)state<=state20;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b10100)state<=

34、state20;else begin out=0;state<=state0;end end endstate21:begin if(count<=1002)begin begin count=count+12'd1;end if(in=5'b10101)state<=state21;else begin out=0;state<=state0;end endelse begin begin out=out;count=0;end if(in=5'b10101)state<=state21;else begin out=0;state<

35、;=state0;end end endstate22:begin out=0;state<=state0;endendcaseendendmodule（2）原理图及仿真波形4、自动播放模块（1）程序设计module huanlesong(in,clk_1M,o1,o2,o3,o4,o5,o6,o7,o8,o9);input in,clk_1M;output o1,o2,o3,o4,o5,o6,o7,o8,o9;reg o1,o2,o3,o4,o5,o6,o7,o8,o9;reg18:0q;reg6:0n;always(posedge clk_1M)if(in=0)begino1=0;o

36、2=0;o3=0;o4=0;o5=0;o6=0;o7=0;o8=0;o9=0;q=q+1;if(q='d200000)begin q='b0;n=n+1;endcase(n)'d1:o3=1;'d2:o3=1;'d3:o4=1;'d4:o5=1;'d5:o5=1;'d6:o4=1;'d7:o3=1;'d8:o2=1;'d9:o1=1;'d10:o1=1;'d11:o2=1;'d12:o3=1;'d13:o3=1;'d14:o2=1;'d15:o2=1;'

37、;d16:begin o1=0;o2=0;o3=0;o4=0;o5=0;o6=0;o7=0;o8=0;o9=0;end'd17:o3=1;'d18:o3=1;'d19:o4=1;'d20:o5=1;'d21:o5=1;'d22:o4=1;'d23:o3=1;'d24:o2=1;'d25:o1=1;'d26:o1=1;'d27:o2=1;'d28:o3=1;'d29:o2=1;'d30:o1=1;'d31:o1=1;'d32:begin o1=0;o2=0;o3=0;o

38、4=0;o5=0;o6=0;o7=0;o8=0;o9=0;end'd33:o2=1;'d34:o2=1;'d35:o3=1;'d36:o1=1;'d37:o2=1;'d38:o3=1;'d39:o3=1;'d40:o1=1;'d41:o2=1;'d42:o3=1;'d43:o3=1;'d44:o2=1;'d45:o1=1;'d46:o2=1;'d47:begin o9=1;o5=1;end'd48:o1=1;'d49:o3=1;'d50:o3=1;'d51:o4=1;'d52:o5=1;'d53:o5=1;'d54:o4=1;'d55:o3=1;'d56:o2=1;'d57:o1=1;'d58:o1=1;'d59:o2=1;'d60:o3=1;'d61:o2=1;'d62:o1=1;'d63:o1=1;'d64:begin o1=0