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1、AT89C51的简况The General Situation of AT89C51Chapter 1 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced periphe

2、ral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a prop

3、er tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multithreadedtest environmentfor thevalidationofitsAT89C51automotive microcontrollers. The goals of thisenvironment was n

4、ot only toprovide a robusttestingenvironmentfortheAT89C51automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT8

5、9C51. The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOSmicrocontrollers are designed to handle high-speedcalculations and fast input/output op

6、erations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments. The automotive industry use MCS 51 microcontrollers i

7、n engine-control systems, airbags, suspension systems, and antilock braking systems (ABS. The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, an

8、tilock braking, and stability control applications. Because of these critical applications, the market requires a reliable costeffective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applicatio

9、ns, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Oncein the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallypro

10、hibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating itacross a productfamily that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with

11、 a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carriedout at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessi

12、tates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides postsilicon system validation (SV of various micro-controllers and processors. The system validation process can be brok

13、en into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16- bittimer/counters, a five vector two-level

14、 interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operationdown to zero frequency and supports two software selectablepowersaving modes. The Idle Mode stops the CPU while allowing the RAM, timer/count

15、ers,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil - lator disabling all other chip functions until the next hardware reset.19 / 18:一曲出PORT Q 苫l*E的FORT D同心三&JFFEB时二网EX由曲匕adcaEE向三TEWPORT 3 LACHPORT 1 LATCHnm附 1 Ml RWMFR二 亚。

16、隆第 AEjrf&TEiaaMD n恬EEQ.AEQlSTiF”所；LirCH二餐PZirpEPFEMJFT SEflUU ROTTJVC T U = = ELOZIGFigure 1-2-1Block DiagramFOFT 3 口印片第1-3Pin DescriptionVCC Supply voltage.GND Ground.Port 0 : Port 0 is an 8-bit open-drain bi-directional I/O port. Asan output port, each pin cansink eight TTL inputs. When 1s are wri

17、tten to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory.In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outp

18、uts the codebytes during program verification. External pullups are required during programverification.Port 1 ： Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urcefour TTLinputs.When 1s are written to Port 1 pins they are pulled high by the i

19、nternal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2 ： Port 2 is an 8-bit bi-directional I/O po

20、rt with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL because of the internal pul

21、lups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program me

22、mory and during accesses to external data memory that use 16-bit addresses (MOVXDPTRIn. this application, it uses strong internal pull-ups when emitting 1s.During accesses to external data memory that use 8-bit addresses (MOVX RI, Port 2 emits the contents of the P2 Special Function Register.Port2 a

23、lso receives the high-order address bits and somecontrol signals durin Flash programming and verification.Port 3 ： Port 3 is an 8-bit bi-directional I/O port with internal pullups.ThePort 3 outputbuffers can sink/sou-rcefour TTLinputs.When 1s are written to Port 3 pins they are pulled high by the in

24、ternal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulledlow will source current (IILbecause of the pullups.Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:RST： Reset input. A high on this pin for two machine cycles wh

25、ilethe oscillator is running resets the device.ALE/PRO：G Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory.This pin is also the program pulse input (PROG during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 t

26、he oscillator frequency,and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped duri-ng eachaccess to external DataMemory.If desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or

27、MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN： Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSENis a

28、ctivatedtwiceeach machine cycle, except that twoPSEN activations are skipped during each access toexternal data memory.EA/VPP： External Access Enable. EA must be strapped to GNDin order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, howev

29、er, that if lock bit 1 is programmed, EA will be internally latched onreset.EA should be strapped to VCC for internal program executions. This pin alsreceives the 12-volt programming enable voltage (VPP during Flash programming, forparts that require 12-volt VPP.XTAL1： Input to the inverting oscilla

30、tor amplifier and input to the internal clock operatingcircuit.XTAL2： Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an on- chip oscillator, as shown in Figur

31、e 1. Either aquartz crystal or ceramic resonator may be used.To drive the devicefrom anexternalclock source, XTAL2 should be left unconnected while XTAL1 is driven as shown inFigure 2.There are no requirements on the duty cycle of the external clock signal, sincethe input to the internal clocking ci

32、rcuitry is through a divide-by-two flip-flop, butminimumand maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripheralsremainactive. The mode is invoked bysoftware. The content of the on-chip RAM and all thesp

33、ecial functions registers remain unchanged during thismode. The idle mode canbeterminated by any enabled interrupt or by a hardware reset. It should be noted that whenidle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycl

34、es before the internal reset algorithm takescontrol.On-chip hardware inhibitsaccess to internalRAM inthis event, but access to theport pins is not inhibited. To eliminatethe possibility of an unexpected write to a port pinwhen Idle is terminated by reset, the instruction following the one that invok

35、es Idleshould not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed.The on-chip RAMand Special Function Registers retain their values until the power-do

36、wn mode is terminated. The only exit from powerdown is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operatinglevel and must be held activelong enough to allow the oscillatorto restart and stabil

37、ize.TheAT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signalsshou

38、ld be set up according to the Flash programming modetable and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals

39、. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-writecycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or unt

40、il the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle.During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true da

41、ta are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.2.1Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate B

42、USY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock b

43、its is achieved by observing that their features areenabled.RSTAT89C514 PROGPlP2.0 P2.3 POP2.eP27ALEP3.6P97X1AL2e7X1AC1RSTGNDRiEN町 89cM*.M - ah+&VPGM MIK f (U号E 10KPULLIJPSiFigure 2-1-1 Programming the Flash Figure 2-2-2 Verifying the Flash2.2 Chip Erase:The entire Flash array is erased electrically

44、 by using the proper combination of control signals and by holding ALE/PROG low for 10 ms.The code array is written with all“ 1 ” s. The chip erase operationmust be executed before the code memory can be re-programmed.2.3 Reading the Signature Bytes:The signaturebytes are read by the same procedure

45、as a normalverification of locations 030H, 031H, and 032H, except that P3.6 andP3.7 must be pulled to a logic low. The values returned areas follows.(030H = 1EH indicates manufactured by Atmel (031H = 51H indicates 89C51 (032H = FFH indicates 12V programming (032H = 05H indicates 5V programming2.4 P

46、rogramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. A microcomputer interface convert

47、s information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some wa

48、y, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter(ADC is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixednumber of possiblebinary values. If

49、the output of the transducer does not vary continuously, no ADC is necessary. In thiscase the signalconditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfac

50、es take a similar form, the obvious difference being that here the flow of information is in the opposite direction。 it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling num

51、bers which may be needed for digital-to- analog converter(DAC. This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified to a form suitabl

52、e foroperating an actuator . The signals used within microcomputer circuitsare almost always too small to be connected directly to the outside world ” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most

53、important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patternsof bits 。 this digital form ismost useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bi

54、t might representthe state of a switch or actuator. To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and

55、processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices,called peripherals, are the CPU s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be

56、used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instruction

57、s to pin may be viewed (or read. by the CPUusing program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communic

58、ation function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.翻译AT89C51的简况1 AT89C51 应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。这些单片机的高速处理速度和增强型外围设备集合使得它们适合于这种高速事件应用场合。然而，这些关键应用领域也要求这些单片机高度可靠。健壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具环境保证了高可靠性和低市场风险。Intel平台工程部门开发了一种面向对象的用于验证它的AT89C51 汽车单片机多线性测