模拟集成电路设计课件英文版basic cmos analog ic design lecture7output stage

1、 index1.general consideration of output stage 1.requirements of output stage 2. output stage design issues 3.non-linearity and harmonic distortion2.general types of output stage 1. Class A MOS source follower 2. Class-A MOS CS stage 3. Class-AB push-pull source follower 4. Class-AB push-pull CS stag

2、e 5. Class-AB quasi-complementary configuration bined common-drain common-source configuration 7.parallel common-source configuration 8.stages using BJTs 9.negative shunt feedback stage. requirements of output stage Provide sufficient output power in the form of voltage or current and be efficientDe

3、liver large output current to low-impedance loads (resistive and/or capacitive). Usually is a voltage buffer, i.e., low voltage gain, high Zin, and low Zout . High Zin is to maintain voltage gain and bandwidth of previous stage. Wide bandwidth if in the feedback loop,Avoid signal distortion. Provide

4、 protection from abnormal conditions (short circuit, over temperature, etc.) output stage design issues Frequency response. Output impedance. Output current. Output voltage range. Power efficiency . signal distortion. non-linearity and harmonic distortionFor a nonlinear system with input x, the outp

5、ut y can be expressed as:y y = = a a0 + + a a1x x + + a a2x x2 + + a a3x x3 + + tvxcos.3cos2coscos.3coscos342cos12cos.coscoscos321033221033322210tbtbtbbttvatvatvaatvatvatvaayWith a pure sinusoidal input non-linearity and harmonic distortion(cont.).43.2133112200vavabvaab.41.21333222vabvabvaabbHD12122

6、2112322.bbbTHDDNDNSSINADThe harmonic distortion factors:The total harmonic distortion21313341vaabbHDThe SINAD is the ratio of signal plus noise plus distortion powers to noise and distortion powers, i.e, Class A MOS source followerA Class A circuit has current flow in the MOSFETs during the entire p

7、eriod of a sinusoidal signal. QSSDDLOUTplyloadIVVRpeakvPPefficiency22sup1. What is class-A ?Characteristics of Class A amplifiers: Unsymmetrical sinking and sourcing Linear Poor efficiencyThe maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%. Class A MOS source follower(cont.)2

8、.circuit: Class A MOS source follower(cont.)LOQDRVII110111/222LWKRVIVVVVVVVVVVLOQfDDoftoOVtogsoi3.distortion in the MOST Source Follower:let VM = VO + VDD + 2f , and assume that ,we can calculate the harmonic distortion factors as follow:tVViisiniMMVVVHD22/12/322116242/12/532164iMMVVVHD Class-A MOS

9、CS stageLDQLOORIIRIV12212121titiOXDVVkVVLWCIitOViIivVVvVV221OVQKVI221221OViOViQLiOVQLLDQOVvVvIRvVkIRRIIVtvviisinOViVvHD41203HDletAssume we can calculate Class-AB push-pull source followerDepends on how the transistors are biased. Class B - one transistor has current flow for only 180 of the sinusoid

10、 (half period). Maximum efficiency occurs when vOUT(peak) =VDD and is 78.5% Class AB - each transistor has current flow for more than 180 of the sinusoid. Maximum efficiency is between 25% and 78.5%1.What is class-AB and class-B ? Class-AB push-pull source follower(cont.)Feed forward class-AB biasin

11、gThe idea of feed forward class-AB biasing:A reference voltage is directly used to drive the sum of the gate-source voltages of the two output source follower;The reference voltage tracks the VDD to obtain a supply voltage independent quiescent current. Class-AB push-pull source follower(cont.)22143

12、/1/1/1/1LWKLWKLWKLWKKPnPn11BQKIIVGS1 + |VGS2| = VGS3 + |VGS4| Class-AB Push-Pull Common-Source StageImproved principle of feed forward biasing for rail-to-rail class-AB output stage: Class-AB Push-Pull Common-Source Stage(cont.)Let IB1 = IB2 = IB3, and1111LWLWK123LWLW1321LWLWK144LWLWThen, VGS1 = VGS

13、11, VGS3 = VGS12, VGS2 = VGS13, VGS4 = VGS14, andIQ = ID1 = ID2 = K IB1 M3 and M4 form a floating resistor. Large output impedance. The pole at Vo can be significant. Large distortion. Usually this output stage is included in the feedback loop.Analysis: Class-AB Quasi-Complementary ConfigurationAAAE

14、NEPttptnVVVLWKLWKLWKnp2121121tgsDVVLWKI22221tgsDVVLWKI Class-AB Quasi-Complementary Configuration(cont.)1) If Vi = 0 and VOSP = VOSN = 0, let ID1 = ID2 = IQ Vgs1 = VtVov Vgs2 = Vt + Vov , then Vgs1 = Vt Vov + AVo (ViVOSP ) Vgs2 = Vt + Vov + AVo (Vi VOSN ) Io =Vo/RL , Io + Id1 + Id2 = 0 LOSNOSPOVOSNO

15、SPiORVVAVALWKVVVV2/112 Class-AB Quasi-Complementary Configuration(cont.)2) If VOSP = VOSN = 0,LmiLOVioRAgVRVALWKVV2112/113) If A(VOSP-VOSN) 1, then221122/112OSNOSPiLmOSNOSPiLOVOSNOSPioVVVRAgVVVRVALWKVVVV Class-AB Quasi-Complementary Configuration(cont.)4）how to calculate the IQ ? 2OSNOSPOSPOVVVV2OSN

16、OSPOSNOVVVV2221OSNOSPOVQVVAVLWKIlet Vi = 0 Class-AB Quasi-Complementary Configuration(cont.) Use of Negative, Shunt Feedback to Reduce the Output Resistance, Can achieve output resistances as low as 10 If the error amplifiers are not balanced, it is difficult to control the quiescent current in M1 a

17、nd M2 Great linearity because of the strong feedback Can be efficient if operated in class B or class ABSummary : combined common-drain common-source configuration combined common-drain common-source configuration (cont.)VOS can be introduced by intentionally mismatching the input differential pair

18、in each error amplifier.The circuit can be designed so that, when Vo = V1 = 0, the introduction of VOS turn off M11 and M12.M11 is turned on only when V1VoVOS |Vtp|/AEP .Error amplifiers, AEP and AEN, can have high gain, and are often designed as onestage amplifier with gain gmro.The wide bandwidth

19、of M1 and M2 source followers simplify the design required to guarantee stability.The V1 voltage range, limited by Vgs3 and Vgs4, can be increased by adding the M6 common-source stage. parallel common-source configuration parallel common-source configuration (cont.) Want turn off M11 and M12 when Vo

20、 Vi = 0, so that AEP2 and AEN2 have high gain, and AEP1 and AEN1 have low gain. VOS of EP1 is introduced by making (W/L)3 0.8(W/L)4 When Vo Vi = 0When |Vi | is small, and M11 and M12 are not turned on, the output is Vo =Vi/1 + 1/(A1gm1RL) When Vi is large, M11 can be turned on, and the output become

21、s Vo ViVOS if AEP2 Define Vi (min) as the minimum input to turn on M11. Vi (min) = VOS(1 + AEP 1gm1RL) if AEP2 M11 and M12 remain o. for only a small range of input voltages. stages using BJTsComments: Can use either substrate or lateral BJTs. Small-signal output resistance is 1/gm which can easily

22、be less than 100. Unfortunately, only PNP or NPN BJTs are available but not both on a standard CMOS technology. In order for the BJT to sink (or source) large currents, the base current, iB, must be large. Providing large currents as the voltage gets to extreme values is difficult for MOSFET circuits to accomplish. If one considers the MOSFET driver, the emitter can only pull to within VBE+VON of the power supply rails. This val