quartus II 软件做4的位乘法器设计

1、用quartus II软件设计4位乘法器1.并行乘法的算法:卜而根据乘法例题来分析这种算法，题中 M4, M3, M2, M1是被乘数，用M表示。N4，N3，N2，N1是乘数，用N表示4/16/20122.乘法模块Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity and4a isPort(a:in std_logic_vector(3 downto 0);en:in std_logic;r:out std_logic_vector(3 downto 0);End and4a;Archi

2、tecture behave of and4a isBeginProcess(en,a(3 downto 0)BeginIf (en=1) thenr=a;Elser=0000”;End if;End process;End behave;-and4a元件源程序library ieee;use ieee.stdjogicl 164.all;use ieee.std_logic_unsigned.all;璀 I,。)一 两仞一entity and4a is丫 g). Q 昌mul4p=1套歹噌琢粉Proit!i_t NavigatorEnti tv * 瓣 and4a.vhd瓣 is283.vh

3、d| 辱 mul4p.vhd。Compilation Fl ep. | 旦 mul4p. vwfl幽 FLEK10K: EFF10K10LC i mul4pdb，加法模块ModulePrugi-tjEE %JS i mill at orLHLibrary ieee;12345678910111213141516171819202122Liljrary ieee;Use ieee . stcl_ 1 gic_ 1164 .all;Use ieee std_1gic_uns igned.a11;H Ent.it.y and4a isP rt- (a: in std_lugic_vector (3

4、dunnt-u u：i ;en: in 3t.Ll_lugic;r : ut stcl_logic_vectur (3 duTiinto u ：i ：i ;End and4a;IS Architect, ur e toe have f ancH a isH BeginPeucess (en,r a (3 duTiintu 0) ：i BeginIf (en= 1 11 ) t-hen rOa;HElser=ULIULI;End if;Encl process;End toehave;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.

5、all;Entity ls283 isPort (o1,o2:in std_logic_vector(3 downto 0); res:out std_logic_vector(4 downto 0); End ls283;Architecture behave of ls283 isBeginProcess(o1,o2)Beginres=(0&o1)+(0&o2);End process;End behave;4.主程序Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity mul4p i

6、sPort (op1,op2:in std_logic_vector(3 downto 0);result:out std_logic_vector(7 downto 0);End mul4p;Architecture count of mul4p iscomponent and4a port (a:in std_logic_vector(3 downto 0); en:in std_logic;r:out std_logic_vector(3 downto 0);End component;Component ls283 port (o1,o2:in std_logic_vector(3 d

7、ownto 0); res:out std_logic_vector(4 downto 0);End component;Signal sa:std_logic_vector(3 downto 0);Signal sb:std_logic_vector(4 downto 0);Signal sc:std_logic_vector(3 downto 0);Signal sd:std_logic_vector(4 downto 0);Signal se:std_logic_vector(3 downto 0);Signal sf:std_logic_vector(3 downto 0);Signa

8、l sg:std_logic_vector(3 downto 0);-signal tmp1:std_logic;Beginsg=(0&sf (3 downto 1);-tmp1op2,en=op1(1),r=se);U1:and4a port map(a=op2,en=op1(3),r=sa);U2:ls283 port map(o1=sb(4 downto 1),o2=sa,res=result(7 downto 3);U3:and4a port map(a=op2,en=op1(2),r=sc);U4:ls283 port map(o1=sc,o2=sd(4 downto 1),res=

9、sb);u5:ls283 port map(o1=sg,o2=se,res=sd);u6:and4a port map(a=op2,en=op1(0),r=sf);result(0)=sf(0);result(1)=sd(0);result(2)=sb(0);-result(7 downto 0) Compilation. | 包 mul4p.vwf | 料 Simulation R. | Pin Planner I 断(roup 5Named:Nude Nameop2r3IniX :-op221Iniop2lOP20毒日 re5ultr7.O=_一II1TOI.CF :- resultr?O

10、lCF resultrfiOl祁 result5TCpVfeWFLBCWKEPFl0K10LC8i-*J.amed:B=| 明 Edit: _xy |PIN_50Filter: |pin：s: eNode NameDirectionLocationReservedGroup1W opl3InputPIN_28opl3.02W opl2InputPIN_29opl3.03 opllInputPIN_30opl3,.0qW opl0InputPIN_35opl3.05W op23InputPIN_47op23.06op22InputPIN_48op23.07W op2lInputPIN_49op23.08op20InputPIN_50op23.09涉 re5ult7OutputPIN_61result7.O10枝 result6OutputPIN_60result7.O11涉 result5OutputPIN_59result7.O12祁 result4OutputPIN_58result7.O13涉 re5ult3OutputPIN_54result7.O14枝 result2OutputPIN_53result7.O15涉 resultlOutputPIN