数字逻辑设计及应用教学课件：8-1 时序电路的设计实践xin

1、c h a p t e r 8Sequential Logic DesignPractices时序逻辑设计实践数字逻辑设计及应用Chapter 88.1 Sequential Circuit Documentation Standards(时序电路文档标准)8.1.4 Timing Diagrams (定时图) and Specifications8.2 Latches and Flip-Flops8.2.1 SSI Latches and Flip-Flops(SSI型锁存器和触发器)applications：8.2.2 Switch Debouncing开关消抖、 8.2.4 Bus Ho

2、lder Circuit总线保持 8.2.5 Multibit Registers and Latches多位寄存器和锁存器CLOCK触发器输出组合电路输出触发器输入建立时间容限Hold-time marginSetup-time margin8.2 Latches and Flip-Flops( 锁存器和触发器)SSI Latches and Flip-Flops1Q 1Q2Q2Q3Q3Q4Q4Q1,2C1D2D3,4C3D4D74x375D LatchesPRD Q CLK QCLR74x74PRJ Q CLK K QCLR74x109PRJ Q CLK K QCLR74x112Switc

3、h Debouncing (开关消抖)+5VSW_LDSWPush(开关闭合)SW_LDSWPush(开关闭合)First Contact(闭合第1次接触)ContactBounce(触点抖动)SW_LDSWIdeal Case (理想情况)SW_LSW0011SW_LSW0011Push(开关闭合)0011SW_LSW0011SW_LSW1100SW_LSWDSWPush(开关闭合)why this circuit should not be used with the high-speed CMOS devices?(为什么不应该同高速CMOS器件一起使用？)QQLS QR Q+5VBus

4、 Holder Circuit (总线保持电路)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSRC0SRC1SRC2P0P1P7SDATA4-bit Register(4位寄存器74x175)6位寄存器74x1741D2D3D4DCLKCLR_L8-bit Register74x374（三态输出）OE输出使能74x377（时钟使能）74x273（异步清零）CLK74x374（输出使能）74x377（Clock Enable, 时钟使能）ENEN二选一多路复用结构 register and latch 寄存器：edge trigger chract

5、erastic 边沿触发特性 锁存器：C有效期间输出跟随输入变化74x374输出使能8位寄存器74x373输出使能8位锁存器8.4 Counters (计数器)Counter(计数器)(P710)The name counter is generally used for any clocked sequential circuit whose state diagram contains a single cycle, as in Figure 8-26. The modulus of a counter is the number of states in the cycle. A cou

6、nter with m states is called a modulo-m counter or, sometimes, a divide-by-m counter. A counter with a nonpower-of-2 modulus has extra states that are not used in normal operation. 计数器的分类按时钟：同步、异步按计数方式：加法、减法、可逆按编码方式：二进制、十进制BCD码、循环码计数器的功能计数、分频、定时、产生脉冲序列、数字运算本节内容行波计数器、同步计数器MSI型计数器及其应用二进制计数器状态的译码8.4.1

7、Ripple CountersAN n-bit binary counter can be constructed with just n flip-flops and no other components , for any value of n. 2bits binary counters normal binary counting sequence is 00-01-10-11-0010108.4.1 Ripple Counterswhen a particular bit changes from 1 to 0, it generates a carry to the next m

8、ost significant bit. The counter is called a ripple counter because the carry information ripples from the less significant bits to the more significant bits, one bit at a time. 00-01-10-11-008.4.1 Ripple Counters（行波计数器） use T flip-flopQ* = QQQT考虑二进制计数顺序：只有当第 i-1 位由10时，第 i 位才翻转。CLKQQTQQTQQTQQTQ0Q1Q2

9、Q3T flip-flop changes state (toggles) on every rising edge of its clock input. Although a ripple counter requires fewer components than any other type ofbinary counter, it does so at a priceit is slower than any other type of binarycounter. In the worst case, when the most significant bit must chang

10、e, the outputis not valid until time n tTQ after the rising edge of CLK, where tTQ is thepropagation delay from input to output of a T flip-flop. Ripple CountersCLKQ0Q1Q2CLKQQTQQTQQTQQTQ0Q1Q2Q3速度慢，最坏情况，第n位要经过 ntTQ 的延迟时间 异步时序8.4.2 Synchronous Counters(同步计数器)A synchronous counter connects all of its f

11、lip-flop clock inputs to the same common CLK signal, so that all of the flip-flop outputs change at the same time, after only tTQ ns of delay. synchronous counter同步二进制加法计数器1 0 1 1 0 1 1+ 11 0 1 1 1 0 0在多位二进制数的末位加 1，仅当第 i 位以下的各位都为 1 时，第 i 位的状态才会改变。最低位的状态每次加1都要改变。EN QT Q 利用有使能端的 T 触发器实现：Q* = ENQ + ENQ

12、 = EN Q通过EN端进行控制，需要翻转时，使 EN = 1 ENi = Qi-1 Qi-2 Q1 Q0EN0 = ? 1synchronous counter1CLKQ0Q1Q2C如何加入使能端？synchronous counter with enable input 有使能端的同步计数器CNTEN低位 LSB高位 MSB串行使能同步二进制加法计数器1 0 1 1 0 1 1+ 11 0 1 1 1 0 0在多位二进制数的末位加 1，仅当第 i 位以下的各位都为 1 时，第 i 位的状态才会改变。最低位的状态每次加1都要改变。对于D触发器：Q* = DDi = (Qi-1 Q1 Q0)

13、QD Q CLK Q= EN Q考虑 T 触发器：Q* = EN Q 利用 D 触发器实现：D0 = 1 Q = Q8.4.3 MSI counters and applicationsMSI型计数器及应用-同步4位二进制计数器74x163CLR同步清零LD同步预置数RCO进位输出ENPENT使能端进位输出清零8.4.3 MSI Counters and Applications4位二进制计数器74x16374x163的功能表01111CLK工作状态同步清零同步置数保持保持,RCO=0计数CLR_LLD_LENP ENT0111 0 1 0 1 174x161异步清零CLKENClear an

14、d load functions同步清零和预置数Q0Q1Q2Q3D0D1D2D3LD_LCLR_LA计数功能的电路Qi* = (Qi-1 Q1 Q0) QQASynchronous clear and load functions同步清零和预置数功能0100000LD_LCLR_LA计数功能的电路Qi* = (Qi-1 Q1 Q0) QQA0010A0A11XSynchronous clear and load functions同步清零和预置数功能LD_LCLR_LA计数功能的电路Qi* = (Qi-1 Q1 Q0) QQAEnables and ripple carry out (RCO) signals使能信号 与进位信号 10010QANQAN1ENP.ENT=1QANLD_LCLR_LB计数功能的电路Qi* = (Qi-1 Q1 Q0) QQB100101QAQBNEnables and ripple carry out (RCO) signals使能信号 与进位信号 Connections for the 74X163 to op