数字逻辑设计及应用教学课件：6-6 比较器 全加器

1、REVIEW OF LAST CLASS译码器编码器三态器件多路复用器奇偶校验器比较器加减器 标准MSI多路复用器 74x151、 74x153、74x157 扩展多路复用器 利用多路复用器实现逻辑函数 多路分配器 利用带使能端的译码器 使能端作为数据输入端REVIEW OF LAST CLASS译码器编码器三态器件多路复用器奇偶校验器比较器加减器 奇校验：输入有奇数个1，输出为1 偶校验：输入有偶数个1，输出为1 利用异或运算实现 9位奇偶发生器74x280 奇偶校验的应用 检测代码在传输和存储 过程中是否出现差错。5.8.2 奇偶校验电路什么是奇偶校验?奇偶校验位+一组信号位基本定理：基本

2、概念：使所有的1加起来为偶数或奇数,来检测系统的方法称为奇偶校验法。A0 A1 An = 1 变量为1的个数是奇数0 变量为1的个数是偶数奇校验电路（odd-parity circuit）如果输入有奇数个1，则输出为1。偶校验电路（even-parity circuit）如果输入有偶数个1，则输出为1。I1I2I3I4INODD菊花链式连接I1I2I3I4IMINODD树状连接奇校验电路的输出反相就得到偶校验电路9位奇偶校验发生器74x280（P291 图575）ABCDEFGHIEVENODD74x280偶数个1时输出为1奇数个1时输出为1Answer key of Home work P5

3、15- 6.666.66 Show how to realize the 4-input, 18-bit multiplexer with the functionality of Table 6-46 using 9 74x153s and a “code converter” with inputs S2S0 and outputs C1,C0 such that C1,C0 = 0011 when S2S0 selects A-B-D-C, respectively. 0001001100100001C1C01D02D0123917D018D03D04D05D06D01Y2Y3Y4Y5Y

4、6Y17Y18YS2S1S0code converterC1C0BA6.67 Design a 3-input, 2-output combinational circuit that performs the code conversion specified in the previous exercise, using discrete gates. Answer key of Home work P515- 6.67S2S1S0code converterC1C00001001100100001C1C0USE karnaugh map !6.9 Comparators（比较器）6.10

5、 Adders, Subtractors, and ALUs(加减器和算术逻辑单元)6.9 comparator（比较器）(P458)比较2个二进制数值并指示其是否相等的电路等值比较器：检验数值是否相等数值比较器：比较数值的大小（,=,B（A=1, B=0）则 AB=1 可作为输出信号 AB3)LT = EQ GT = ( EQ + GT )或 (A3 = B3) (A2 = B2) (A1B1)或 (A3 = B3)(A2 = B2)(A1 = B1) (A0B0)或 (A3 = B3) (A2B2)A3 B3A2 B2A1 B1A0 B0+输出高有效!74x856.9.4 Standard

6、 MSI Comparatorsthe 74x85 4-bit comparator A0A1A2A3ALTBINAEQBINAGTBIN级联输入，用于扩展ALTBOUT = (AB高位A高位=B高位 & A低位B低位ABAEQBOUT = (A=B)AEQBINAGTBOUT = (AB) + (A=B)AGTBIN74X85Serial Expanding Comparators(比较器的串行扩展)XD11:0YD11:03:07:411:8XY+5VABIABOA0A3B0B374x85ABIABOA0A3B0B374x85ABIABOA0A3B0B374x853片74x85构成12位比

7、较器低位高位Digital Logic Design and Application (数字逻辑设计及应用)8-bit comparator 74x682 (P463)P0P1P2P3P4P5P6P78-bit comparator 74x682(P463)问题1：怎样用输出来表示下列条件？ DIFF高电平有效：P DIFF Q EQ高电平有效：P EQ Q GE高电平有效：P GE Q LT高电平有效：P LT Q （P463 Figure 6-80）GELT问题2：能否扩展？注意：没有级联输入端3片74x682构成24位比较器P0P7 P=QQ0Q7 PQP0P7 P=QQ0Q7 PQP0

8、P7 P=QQ0Q7 PQ7:015:823:16P23:0Q23:0PEQQPGTQParalel Expanding Comparators(比较器的并行扩展)exercise Design a circuit to compare three 4-bit binary numbers A(a3a2a1a0), B(b3b2b1b0), C(c3c2c1c0) with two 4-bit comparators 74X85. You need to give three outputs: Fequal, FAmax, FAmin. Fequal =1 indicates A=B=C; F

9、Amax =1 indicates A is the biggest one among them; FAmin =1 indicates A is the smallest one among them. Show your work. (You can finish your design with some other gates you think necessary. ) 6.10 Adders, Subtractors, and ALUs (加减器和算术逻辑单元) (P471)6.10.1 half adders and full adders 半加器和 全加器 (P474)概念：

10、能对两个1位二进制数进行相加而求得和及进位的逻辑电路称为半加器。概念：能对两个1位二进制数进行相加并考虑低位来的进位，即相当于3个1位二进制数相加，求得和及进位的逻辑电路称为全加器。 SCOXYCIS = X Y CIXY00100111CIXY00 01 11 1001COXCICO = + +YCI= XY + (X+Y)CI0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1CIXYSCO全加器真值表6.10.2 Ripple Adders串行进位加法器缺点：运算速度慢，有较大的传输延迟tADD

11、= tXYCout + (n-2)*tCinCout + tCinSX YCI COSX YCI COSX YCI COSX YCI COSC1C2C3C4C0S0S1S2S3X0 Y0X1 Y1X2 Y2X3 Y3=0回顾：串行比较器 提高速度：并行加法器X YCI COSX YCI COSX YCI COSX YCI COSC1C2C3C4C0S0S1S2S3X0 Y0X1 Y1X2 Y2X3 Y3X YCMPEQI EQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11X YCMPEQI EQOX YCMPEQI EQO串行比较器串行加法器主 输 入主 输 出边界输入边界输

12、出级联输出迭代电路（iterative circuit）Iterative：重复的, 反复的, 数迭代的PICI COPOPICI COPOPICI COPOC0C1C2CnPO0PO1POn-1主 输 出PI0PI1PIn-1主 输 入边界输入边界输出级联输出P297一位全加器：S = X Y CiCi+1 = XY + (X+Y)Ci6.10.4 Carry Lookahead Adders并行进位加法器超前进位法：第 i 位的进位输入信号可以由该位以前的各位状态决定。Ci+1 = (XiYi) + (Xi+Yi) Ci= Gi + Pi Ci进位产生信号进位传递信号0 0 0 0 00

13、0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1CiXYSCi+1全加器真值表6.10.4 Carry Lookahead Adders并行进位加法器Ci+1 = (XiYi) + (Xi+Yi) Ci= Gi + Pi Ci进位产生信号进位传递信号6.10.5 MSI Adders(P479 )6.10.6 MSI Arithmetic and Logic Units (ALU, MSI 算术逻辑单元)Perform any of a number of different arithmetic and logical

14、 operations on a pair of b-bit operands.(对2个b位的操作数进行若干不同的算术和逻辑运算)S0S3MCINA0A3B0B3GPF0F3COUTA=B74x181输入数据输出数据0算术/1逻辑选择特定操作P483 Table 6-7074x181 (P483)2 examples of 74x148.Answer key of homework6.52 Draw the logic diagram for a circuit that uses the 74x148 to resolve priority among eight active-high i

15、nputs, I0I7, where I7 has the highest priority. The circuit should produce active-high address outputs A2A0 to indicate the number of the highest-priority asserted input. If no input is asserted, then A2A0 should be 111 and an IDLE output should be asserted. You may use discrete gates in addition to

16、 the 148. Be sure to name all signals with the proper active levels. 设计判定优先级电路：（利用74x148 ） 8个输入I0I7高电平有效，I7优先级最高 地址输出A2A0，高电平有效 如果没有输入有效，输出为000且输出IDLE=1有效I7I0A2A1A0IDLEA2A1A0GSEOEII7I074x148若没有输入有效，地址输出为111且输出IDLE=1有效,电路需变化.见下页!设计判定优先级电路：（利用74x148 ） 8个输入I0I7高电平有效，I7优先级最高 地址输出A2A0，高电平有效 如果没有输入有效，地址输出

17、为111且输出IDLE=1有效I7I0A2A1A0GSEOEII7I074x148P514 6.52A2A1A0IDLEAnswer key of homework6.53 Draw the logic diagram for a circuit that resolves priority among eight active-low inputs, I0_LI7_L, where I0_L has the highest priority. The circuit should produce active-high address outputs A2A0 to indicate the number of the highest-priority asserted input. If at least one input is asserted, then an AVALID output should be asserted. Be sure to na