数字逻辑设计及应用教学英文课件：Lec12-Chap 6

1、1Digital Logic Design and ApplicationLecture #12Chapter 6 Combinational Logic Design PracticesEncodersUESTC, Spring 20136.5 EncodersThe process of using binary codes for a particular signal is called encoding.用二进制代码代表特定的信号的过程就叫编码。21. Encoder特定的物理含义的信号已经为某种数字信号Multiple-Input, Multiple-Output Logic Ci

2、rcuit6.5 EncodersEncoders discussed in this course一般是将十进制码转换为相应的其它编码，其实质与代码转换译码器一样。Binary encoder（二进制编码器）Output code has fewer bits than its input code.2n-to-n encoder31. Encoder46.5 EncodersBinary Encoder A0A1A2I0I1I71 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1

3、 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7A2 A1 A0Truth Table for a 8-to-3 EncoderOne out-of-2nn bit binary8-to-3 EncoderGuarantee:At most one input is asserted at any time.任何时候只有一个输入有效28种可能的输入组合中只有8种组合是有效的。56.5 EncodersA0 = I1 + I3

4、+ I5 + I7A1 = I2 + I3 + I6 + I7A2 = I4 + I5 + I6 + I71 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7A2 A1 A0Truth Table for a 8-to-3 EncoderGuarantee:At mos

5、t one input is asserted at any time.任何时候只有一个输入有效8种有效的输入组合中，任何时刻只有一位输入是有效的66.5 EncodersThe trouble:When more than one inputs are asserted? assign priority to the input Request encoder REQ1REQ7REQ2Requestsfor servicerequestors numberA0 = I1 + I3 + I5 + I7A1 = I2 + I3 + I6 + I7A2 = I4 + I5 + I6 + I7Gua

6、rantee:At most one input is asserted at any time.71. Priority EncoderA2A1A0IDLEI7I6I5I4I3I2I1I0Outputs A2A0 contain the number of the highest priority asserted input. How to decide the priority? define intermediate variables H0H7, H7 = I7H6 = I6 I7H5 = I5 I6 I7H0 = I0 I1 I2 I6 I7I7 has the Highest-P

7、riorityHi is asserted if Ii input is asserted and Ii has the highest priority.优先级高于它的输入端必需无效优先级低于它的输入端不考虑（任意）81. Priority EncoderA2A1A0IDLEI7I6I5I4I3I2I1I0Outputs A2A0 contain the number of the highest priority asserted input. I7 has the Highest-Priority IDLE output is asserted if no inputs are asse

8、rtedIDLE = I1 I2 I6 I7 A2 = H4 + H5 + H6 + H7A1 = H2 + H3 + H6 + H7A0 = H1 + H3 + H5 + H792. The 74x148 Priority Encoder data inputsaddress outputsEnable Output,EOGroup Select GS没有输入请求时有效 Enable Input EI有输入请求时有效 All inputs and outputs are active low.EI无效时，任何输出均无效 EI有效GS=EOIDLE10Table 6-27 Truth tabl

9、e for a 74x148 8-input priority encoder11Tow 74x148s cascaded to handle 16 requestesQiY3 Y2 Y1 Y0Truth Table for a 16-to-4 EncoderQ15Q8Q7Q0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0Chip 1Chip 0Chip 1工作,Y3有效;Chip 0工作,Y3无效。Y3应该与片1工作时始终保持有效的信号相连。Y3GS1片0或片1的任意输入请求有效，输出Y2Y1有效。Chip1和chip0的A2A1均与Y2Y1相连，片1的Ai与片0的Ai是或

10、的关系。Y2Y1A2A112A2A1A0GSEOEII7I0A2A1A0GSEOEII7I0Chip 0Chip 1Q15_LQ8_LQ7_LQ0_LY0Y1Y2Y3GSTow 74x148s cascaded to handle 16 requestes片间优先Tow 74x148s cascaded to handle 16 requestesConsiderationsHow many chips is needed16/8=2 chips are needed, At any time only one chip is working, et. priority-among-chip

11、(片间优先)EI for lower chip is asserted if EO for higher chip is deasserted output expand4 address outputs to build a 16-4 priority encoderlower 3 bits (Y0Y2)- priority-in-chip(片内优先)Highest 1 bit (Y3)-higher chip select GS1(片间优先)One GS outputGS is asserted if any chip is assertedGS= GS1+ GS0 131432-inpu

12、t priority encoderRA4RA3RA2RA1RA0RGSRI7_L RI0_LRI15_L RI8_LRI23_L RI16_LRI31_L RI24_L4-to-2encoderEI A2A0 GSI7I0 EOEI A2A0 GSI7I0 EOEI A2A0 GSI7I0 EOEI A2A0 GSI7I0 EO0123151 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1GS0 GS1 GS2 GS3A4 A34-to-2 encoderA3 = GS3 + GS1A4 = GS3 + GS2012332-inputpriority e

13、ncoder16输入：由864，需8片74x148每片优先级不同（怎样实现？） 保证高位无输入时，次高位才工作 高位芯片的EO端接次高位芯片的EI端A2A1A0GSEOEII7I0片间优先级的编码 利用第9片74x148 每片的GS端接到第9片的输入端 第9片的输出作为高3位（RA5RA3） 片内优先级 片间优先级 输出：6位 低3位 高3位 8片输出A2A0 通过或门作为 最终输出的低3位 RA2RA0 用74x148级联为64-6优先编码器17I0_LI7_LA2A1A0AVALIDExample 2. Analysis the following circuitP514 6.53 8 a