前瞻网路安全处理器及相关SOC设计与测试技术研发ppt课件

1、Network Security Processor and the Related SOC Design and Test Technologies Bist for RAm IN SecondsJuly , 2006Memory Testing Problem & SolutionsProblem: memory manufacturing is not perfectNeed testing, diagnosis, and repairRAMSES: RAM/Flash fault simulatorTAGS: RAM/Flash test algorithm (pattern) gen

2、eratorBRAINS: RAM BIST generatorFAME: memory failure analyzerDesign(Layout)DefectInjectionFaulty Cell BehaviorFaultModelsFaultModelsTestAlgorithmsBuilt-InSelf-TestBuilt-InSelf-RepairTester2Memory BIST Automation FlowBRAINS:BIST for RAMs in SecondsBISTIntermediateDescriptionSimulation/Synthesis/P&R F

3、lowBRAINSgbrainsMemory LibraryBIST TemplatesBID ConstructorCompiler KernelBIST DesignActivation SequencesIntegration ScriptsMemory SpecTest RequirementMemory CompilerIPGeneratorsCommandScriptsGUI3Test Schedule and Test GroupingSingle-portSRAMGroup 0ControllerSequencer 1Dual-portSRAMGroup 12R1WRegist

4、er FileSingle-portSRAMRead portWrite portRead-write portSequencer 0Group 0Parameters:Memory typeMemory spec.Power constraintUser define4Algorithm Programming & Test Scheduling5Driving Capability & Pipeline Optimization6BIST Circuit Generation FlowMemory Info.Test AlgorithmTest SchedulingDriving/Timi

5、ng Spec.BIST CompileStartRTL, TB, Syn. ScriptMemory model, address, word widthDefault / ProgrammableAuto / User definedPin loading, latencyBID7BIST ArchitectureMemoryBISTExternal TesterMBSMSIMBOMRDMSOMBCMBRMCKControllerRAMRAMRAMRAMRAMRAMSequencerSequencerSequencerTPGTPGTPGTPGTPGTPG8Experiment Result

6、 & ComparisonMemory Spec:64 X 64: 2 modules64 X 128: 3 modules512 X 64: 1 module512 X 128: 2 modulesFull speed testing - clock rate: 100 MHzDiagnosis functionTest algorithm: March C- (Mentor), March CW (BRAINS)Test time(cycle)Gate countBRAINS2,423,50028,910Mentor20,080,90030,3539FAMEFAME: Failure An

7、alyzer for MemoriesMECA: Memory Error Catcher and AnalyzerRAMSES: RAM fault simulatorTAGS: RAM test algorithm generatorERA: RAM error analyzerMDD: Memory Defect Diagnosis ToolAFA: Automatic Fault AnalyzerFPA: Failure/Fault Pattern AnalyzerGUI-based Failure/Fault Pattern Viewer10FAME: Failure Analyze

8、r for Memory11Realistic Defect InjectionPurpose: to determine if a circuit is damaged by a certain defectOpen DefectsShort DefectsDContact/ViaMissing ContactD12Diagnostics Using Fault PatternsA cause-effect approach:Fault PatternsDefectiveNetlistRealistic FaultPatternsPrediction StageApplication Sta

9、geSimulationReductionDefectDictionaryDefect Candidates13Fault Pattern Analysis Results14Memory Defect Diagnostics (MDD)Memory Defect Diagnostics15Failure/Fault Pattern Viewer16SummaryFault-pattern oriented methodology for defect diagnosticsLayout-based defect injection and defect dictionary creationCombines strengths of conventional failure-pattern approach and our fault-type approachIntegrated memory failure analysis frameworkCost-effective defect identification and yield impr