空间科学与应用研究中心

1、Assignment1. Design an 8-bit upand downsynchronouscounter inVHDLwith thefollowing(1) The same portsAssignment1. Design an 8-bit upand downsynchronouscounter inVHDLwith thefollowing(1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-s(2

2、) The counter is with an asynchronous t assigns a specific initial value (3) The counter is synchronous data load control input for a new value of and an enable control input for allowing the up and down counting. The load input has a priority over the enable control input. This t when the operation

3、 isin sthe counter operationis(4) Some ypes, such as STD_LOGIC, UNSIGNED, SIGNED EGER, may Synthesize the design. Create a set of reasonable input waveforms for your design completeboth behavioral t-place&routesimulationsernalsignalsand/orincluded in waveformorlist 1、题目使用VHDL-所inout 8 bit reset 端口、l

4、oad 端口，load 先级比enable即 counterenable8 bit 8bit2、程序2、程序library use use entitycounter_bidirport inininstd_logic; up_down: instd_logic; incnt_inout: inoutstd_logic_vector(7downtoend architectureBehavioralofcounter_bidirsignalcnt_in: std_logic_vector(7downtosignalcnt_out:std_logic_vector(7downto0); 3、Te

5、st -signaloe:3、Test -signaloe:std_logic:=0; signalload:std_logic :=load0,cnt_inout 为输出enable=currenttime:400ns wait for 300 ns;load=-当 t_inout作为输入时(把 t_inoutcnt_incnt为高阻状态-否则，即cnt_inout作为输出时(把 t_out(即计数器计数输出值)-end s(load,cnt_out,cnt_inout) if (load=1) cnt_inoutZ); cnt_in = cnt_inout;cnt_inout=cnt_ou

6、t; end if;end -counter_control: s(clk,-当复位信号rst=1,cnt_out否则在时钟的上升沿检测 t_inout-当作为输入时load=1 ), 把cnt_in中的数取进来-end s(clk,rst) if (rst = 1)cnt_out0);elsif rising_edge(clk)if (load = 1) thencnt_out = cnt_in; elsif(enable=1) thenif (up_down = 0) then cnt_out=cnt_out+1;cnt_out=cnt_out-1; end if;endif; end if;end 4功能仿真（前仿4功能仿真（前仿真根据TestBench进入程序之后，首先复位，这时cnt_out 0 4 之后，把 cnt_inout 变成了输入信号，并且给其赋了10000011；在load 加载该值之后，200ns 之后将cnt_inoutcnt_inout131100ns129(时50 ns)，然后遇到了up_down=0，开始做递增。5、ISim 时序仿真（后仿真在ISE Prope PropertiesFPGA，仿真器（Simulator）选择为“ISim在仿真（Simulation）下拉列表中，选择在ISim在后仿真的波形中，可以看到输出（输入）信号cnt