modelsim新手入门仿真教程

Modelsim新手入门仿真教程1．打开modelsim软件，新建一个library。MMadelSimSE-6410.4FileEdrtView匚ompileFileEdrtView匚ompileNewOpen.**LoadCloseProjectImportExpert►SaveCtrl45FolderSource卜Project-.HelpLibrary.DebugArchive十IReaJtsAnaiysrs□占.SimulateAddProjectTookL劭2.library命名XLixa-yName：LbraryPhysicalName：UEKtGixeIIXLixa-yName：LbraryPhysicalName：UEKtGixeIIjCj匚reate日NewLibraryCreatez；q色州hbr吕rvP"amaptoartxtstirtglibraryP"an已vlibraryandalogicalmappingtcit3.新建一个工程。AleEditViewCompile^imuhteAddProject「口口1$NewFolderOpen.,,Source卜7ba^d卜Prqjed:...J6derseProjectLtrary„.Import►Debug；Archive.PB1LExpert卜ResultsAralvssDatabase,Save匚訊特SaveAs…Report.”f'harin&nirar+rwu*XVQ匚anu凸CopySettingsFrom0,4/exajq:Le5Z^iixielsijnxiniBrowse…|•Cop7LibraryMappings”ReferenceLibraryMapomgsC：/modeltech6410.i/exaicplesL^xarYNameMCreateProjectProjectLocationBrowse^3.出现下面界面，点击close。4.新建一个verilog文件SimijlateAddProjectTool?LayoutBookmarks讥SimijlateAddProjectTool?LayoutBookmarks讥FileEditViewCompileNewOpen.”TOC\o"1-5"\h\zLoad1CloseProjectImpcrt1Expert1SaveCtrl+SSaveAs…Report...rWi&rty'kruFolderSoltmProject-“Library.,.DebugArdirve...ResuHsAraR銅Database-4.键入主程序。下面以二分之一分频器为例四ihapri-I卑rftjj'C:hv出1站£4_0^taDMte^IjrlM-Lv-Made■—IE]nMjulthjlf_eLlIEeMr^clt^ia.Elk_MHI?丄护g<s】k_】mi^FC办]|outpreE]k_CHrE.ri『Egjwt；5|*iw^a9iDh^vdirvclk_i<申bcg-lniIli|!Etam鼻Clt_CIM：*CJ*Iifigip1：elh_3OE"-cli_-3utrr*M:L文件代码：modulehalf_clk(reset,clk_in,clk_out);inputclk_in,reset;outputclk_out;regclk_out;always@(negedgeclk_in)beginif(!reset)clk_out=0;elseclk_out=~clk_out;endendmodule编辑完成后，点击保存。EjzlAllCclumnsM亂ikimnLayoutFileEdit^/iewCompileSimulateAddSourceToolsEjzlAllCclumnsM亂ikimnLayoutFileEdit^/iewCompileSimulateAddSourceToolsStatuhyreIOrdeiModified1^1Project^NameMA?保萍在CD楼翌日朝快逹话问CJM35IXC^wincfows.drilgmMA?保萍在CD楼翌日朝快逹话问CJM35IXC^wincfows.drilgmmixedh>ngpsJ■syrtemc巒怯rwerik>gitext203&/7/<11^42020/7/411:042020/7/411^4£020/7/411KM2D20/7/4112025/7/411^2D20/7/411;042QKJ/7/411:042020/T/411:042020^/723:162020/7/411:04HinTflbrt1FP.M11文件老⑷：W3B性存绘3〔卄：文件名要与module后面的名称相同。5•再新建一个测试文件，步骤同上面新建的主程序文件，文件名后缀改为.vt程序代码如下：'timescale1ns/100ps'defineclk_cycle50moduletop;regclk,reset;wireclk_out;always#'clk_cycleclk=~clk;initial

beginclk=0;reset=1;#10reset=0;#110reset=1;#100000$stop;endhalf_clkm0(.reset(reset),.clk_in(clk),.clk_out(clk_out));Endmodule6.添加文件，编译文件先右键点击左边空白处，选择addtoproject—existingFileFileEditSew匸口mpileSirnulat?AddProjectTodsLayufBoDlcmarkiWh-hJctwHelp

画盂丨x脈爼口二丨莎」料生］|炒|翥］|魯塾幽璘僵”tIftC\/!KdHtKho4_lQ.4^7MT0iM1tl£_Cyd*s--DtIWjft't^macdle丄n97JQC>R3defic-Ecit_cy€ieMnoduletcprU丄thniretjwirecll_cu£;iLlviyafelk:_c：^cleMAyI出UnlUilXWC13E-3Jrtser-l"1-10EeseQ-0,!I1J.Qrcwt-1：flOOGCFOiSTcp-tud［^1hBif_cliEfiij选择刚刚新建的两个文件。按ctrl键可以同时选择两个，选择打开，下一步点击ok7选中其中一^，右键，选择complieTcomplieall7/20201L1J3I5LCofnpilePropei'bes,,.ProjectSettings,*Na™匚ompileAddtoProjectRemovefi'omPtojectCofnpileOjtof-D&teCloseProjectCompileOrder,nHUpdateCcmpdeReport...PropeitM.匚ompileSurnrnary.r.Stati^TypeOrdsModifieddk_tYde.vtMtExecvtef/07/202011:39:52…con^ileAll出现两个勾，说明编译通过。出现x,说明文件编译出错，双击x,可以查看错误。MModelSimSr-6410.4FileEditView匚ompileSimulateAddProjectTool?LayoutB凸ProjectFileEditView匚ompileSimulateAddProjectTool?LayoutB凸Projectdkrl^arne8.终于可以仿真了选择simulate^startsimulateMModelSimSE-6410.4FileEdrtViewCompile*晉|黄〔ColurnnLayout|a11Co1ueiisHelpMFileEdrtViewCompile*晉|黄〔ColurnnLayout|a11Co1ueiisHelpM③酗X#SimulateAddProjectToolsLayoutBookmarksWindcDesignOptinirzatjori-,.Start5<miJaticn.^RGntMT*eOptions-*.StegRestart...BreakEndSimulation33：51...选择刚刚新建的库里面的top,或者测试文件名称，左下角的enableoptimization—定要去掉勾，有勾的画不会出来波形，一定要去掉勾！一定要去掉勾！一定要去掉勾！（本人也不清楚原因，都是初学者，嘻嘻）MStartSimuhtioriXDesign]VHDL]Verilog]Libraries]5DF]Others]TNann亡TvcePath+血Yak-■£text_]half_ckTNann亡TvcePath+血Yak-■£text_]half_ck”topftoatfixlfcie&e_env(empty)infactncZjib(empty)mgc^ams(empty)mtiAvmLibraryLbraryModuleworkC:/modelte±64_10.4/exarnples/tExtC:/m&deltech64_10.斗足xarnples/half_dk