数字电路与逻辑设计 基于VHDL的数字逻辑设计

基于VHDL的数字逻辑设计组合逻辑部分组合逻辑电路设计分析逻辑问题，抽象输入、输出逻辑变量。列真值表、写函数表达式。采用基本门电路、PLD实现。实体描述ENTITY__entity_nameIS PORT( __input_name :IN STD_LOGIC; __input_vector_name:INSTD_LOGIC_VECTOR(__highdownto__low); __output_name, :OUT STD_LOGIC); __output_vector_name:OUTSTD_LOGIC_VECTOR(__highdownto__low);END__entity_name;ARCHITECTUREaOF__entity_nameIS

SIGNAL__signal_name:STD_LOGIC;BEGIN --ProcessStatement --ConcurrentProcedureCall

--ConcurrentSignalAssignment --ConditionalSignalAssignment --SelectedSignalAssignment --ComponentInstantiationStatement --GenerateStatementENDa;结构体描述（1）编码器（2）译码器（3）比较器（4）数据选择器（5）三态输出电路

常用组合逻辑电路设计（1）编码器A6A7A5A4A3A2A1A0Y2Y1Y08×3编码器ENA7A6A5A4A3A2A1A0Y2Y1Y00000000100000000010001000001000100000100001100010000100001000001010100000011010000000111libraryieee;useieee.std_logic_1164.all;entitybmqisport(A:instd_logic_vector(7downto0);En:in

std_logic;Y:outstd_logic_vector(2downto0));endbmq;architecturem1ofbmqissignalsel:std_logic_vector(8downto0);beginsel<=En&A;withselselectY<="000"when"100000001","001"when"100000010","010"when"100000100","011"when"100001000","100"when"100010000","101"when"100100000","110"when"101000000","111"when"110000000","000"whenothers;endm1;architecturem2ofbmqissignalsel:std_logic_vector(8downto0);beginProcess(En,A)BeginIfEn='1'thenifA="00000001"thenY<="000";

elsifA="00000010"thenY<="001";

elsifA="00000100"thenY<="010";

elsifA="00001000"thenY<="011";

elsifA="00010000"thenY<="100";

elsifA="00100000"thenY<="101";

elsifA="01000000"thenY<="110";elseY<="111";endif;ElseY<="000";endif;endprocess;endm2;（2）译码器A.3－8译码器3×8译码器A6A7A5A4A3A2A1A0Y2Y1Y0ENlibraryieee;useieee.std_logic_1164.all;entityymqisport(Y:instd_logic_vector(2downto0);EN:instd_logic;A:outstd_logic_vector(7downto0));endymq;architecturem1ofymqissignalsel:std_logic_vector(3downto0);beginsel<=En&Y;withselselectA<="00000001"when"1000","00000010"when"1001","00000100"when"1010","00001000"when"1011","00010000"when"1100","00100000"when"1101","01000000"when"1110","10000000"when"1111","11111111"whenothers;endm1;

B.码制转换（2）译码器四位二进制码转换为BCD码，并译码显示。

（数码管为共阴极）Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitybcdisPort(A:instd_logic_vector(3downto0);bcd0,bcd1:outstd_logic_vector(3downto0);seven0,seven1:outstd_logic_vector(6downto0));Endbcd;Architectureaofbcdis

signaltmp:std_logic_vector(3downto0);Beginbcd0<=Awhen(A<10)elseA+6;bcd1<=“0000”when(A<10)else“0001”;tmp<=bcd0;

seven0<="0111111"whentmp="0000"else

--0

"0000110"whentmp="0001"else

--1

"1011011"whentmp="0010"else

--2

"1001111"whentmp="0011"else

--3

"1100110"whentmp="0100"else

--4

"1101101"whentmp="0101"else

--5

"1111101"whentmp="0110"else

--6

"0000111"whentmp="0111"else

--7

"1111111"whentmp="1000"else

--8

"1101111"whentmp="1001"else

--9

"0000000";seven1<=“0111111”when(A<10)else“0000110”;Enda;（3）比较器AGTBBLTBAEQBAB如果a>b，输出为：agtb=‘1‘，altb=’0’，aeqb=‘0’;如果a<b，输出为：altb=‘1‘，agtb=’0’，aeqb=‘0’;如果a=b，输出为：aeqb=‘1‘，agtb=’0’，altb=‘0’。Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;ENTITYcmpabIS

PORT(A,B:instd_logic_vector(7downto0); AGTB,ALTB,AEQB:outstd_logic); ENDcmpab;ARCHITECTUREaOFcmpabISBEGIN

aeqb<='1'whena=belse'0';agtb<='1'whena>belse'0';altb<='1'whena<belse'0';ENDa;ARCHITECTUREbOFcmpabISBEGIN

process(a,b)begin

ifA>Bthenagtb<='1';

elsifA=Bthenaeqb<='1';

elsealtb<='1';endif;

end

process;ENDb;（4）数据选择器4选1MUXABCDYS0S1libraryieee;useieee.std_logic_1164.all;entitymux41isport(A,B,C,D:instd_logic;sel:instd_logic_vector(1downto0);dout:outstd_logic);endmux41;architecturearchmuxofmux41isbegin

withselselectdout<=Awhen"00", Bwhen"01", Cwhen"10", Dwhenothers;endarchmux;

（5）三态输出电路

AENBEN=1B=A;EN=0B=高阻态libraryieee;useieee.std_logic_1164.all;entitytrioutisport(data_in :instd_logic;en :instd_logic;data_out:outstd_logic);endtriout;architecturebehaveoftrioutisbegin

data_out<=data_inwhenen='1'else'Z';endbehave;

--注意此处的“Z”要大写；libraryieee;useieee.std_logic_1164.all;entitytrioutisport(data_in :instd_logic_vector(7downto0);en :instd_logic;data_out:outstd_logic_vector(7downto0));endtriout;architecturebehaveoftrioutisbegin

data_out<=data_inwhenen='1'

else(others=>'Z‘);

endbehave;

--注意此处的“Z”要大写；总结：VHDL+PLD组合逻辑电路设计逻辑问题逻辑输入、输出，逻辑函数逻辑输入描述：1位的输入变量标准逻辑类型，std_logic多位的输入变量标准逻辑序列类型，std_logic_vector逻辑输出描述：同逻辑输入。逻辑关系描述：列出真值表

适用于输入变量较少、或函数有效输入值较少的情况。求取逻辑函数表达式输出变量较少或输出变量相互独立的情况。逻辑关系直接表述（逻辑关系概括直接逻辑描述）

码制转换等问题（数值运算类）例一：四位二进制数转换为BCD码。entitybcd2bisport