计算机组成全册配套完整课件

计算机组成(英文版）全册配套完整课件TextbookandReferenceComputerOrganization&ArchitectureDesigningforPerformance(SeventhEdition)ByWilliamStallings计算机组织与体系结构性能设计（第7版）张昆藏译计算机组成与结构（第4版）王爱英主编计算机组成原理（第4版）白中英主编WebresourcesWillamS/COA/COA7e.htmlWillamS/StudentSupport.htmlIntelDeveloper’sPagePowerPC:Motorola&IBMTop500SupercomputerSiteCourseFeaturesWhataboutthiscourseSpecifythecomputerarchitectureandcomponentsHowtoorganizethesecomponentsBestoptimizingtheperformanceofwholecomputerMaincoursesinvolvedDigitalLogicOperatingSystemComputerInterfaceAssembleLanguage

Whyisthiscourseneeded?FundamentalcourseforprogrammerAcoursecontainingmorehardwarethansoftwareInstructionforfurtherlearninghardwareTheideasandprinciplescontainedinthiscoursecanbeoftenusedinprogrammingCommonknowledgeProgrammershouldholdnecessaryhardwareofcomputerStudyingmethodsAttendlectureearnestlyReviewanddigestintime(justaftertheclass)CompleteourhomeworkFrequentlyconsulttherelatedWebsiteandknowaboutthelatestinformationExaminationFinalmark：Experiment：20%Homeworkandattitude：10%Finalexam：70%Attitudeisanything!GoalsSpecialtyandprofessionalEnglishReadingcarefullythebookRememberthebasicconceptsandimportantprinciplesAfterourclass,wecanreadscienceandtechnologyliteratureswithoutdictionaryWritedissertationabstractContentsPart1:OverviewPart2:ComputersystemPart3:CPUPart4:CUPart5:Parallelorganization17chaptersPartOne:OverviewChapter1:IntroductionIntroducingthecomputercomponentsandtheirfunctionsChapter2:ComputerEvolutionandPerformance1.1Organization&ArchitectureComputerarchitecture:Ch.1–1.1Computerarchitecture:Def.1：designoftheabstractionlayersthatallowustoimplementinformationprocessingapplicationsefficientlyusingavailablemanufacturingtechnologies.Def.2：attributesvisibletoaprogrammerTheseattributeshaveadirectimpactonthelogicalexecutionofaprogramConceptualstructureandfunctioncharacteristicCh.1–1.1ComputerOrganizationDef.1：implementandinterconnectoperationunits(components)specifiedinarchitecture

Def.2：FundamentalattributesvisibletoasystemdesignerAnimplementationofthearchitecture

Ch.1–1.1Computerarchitecturereferstologicaldesignofacomputer;whilecomputerorganizationisimplementationofthislogicaldesignForexample,whetheracomputerwillhaveamultiplicationfunction,itisanarchitectureissue;whilehowtoimplementthemultiplierbelongstotheorganizationconceptCh.1–1.1ComputerImplementationsDef.1:

physicalImplementationsofcomputercomponentsinorganizationDef.2:Thehardwareoutofwhichwemakecomputersystems.Transparency/Transparent:Forexistedthingsorattributes,fromapointofview,theyarelookedasnotexisted,thisconceptiscalledtransparencyCh.1–1.1Architecturalattributes:{instructionset，wordlength，I/Omechanism，addressing，etc}Organizationalattributes:{controlsignal，interface，memorytechnology，bustechnology，…hardwaredetailstransparenttoprogrammer}Implementattributes:{IntegratedCircuits(ICs),PrintedCircuits(PC)

boards,PowerSupplies,Chassis,Connectorsand

Cables，etc}Ch.1–1.1SeriesComputers:computerswiththesamearchitectureanddifferentorganization(Software)compatibility/compatible:Thesoftwarecanoperateinallcomputerswiththesamearchitecture.Theresultisthesame,differenceexistsinrunningtimeCh.1–1.1Upwardcompatibility：programforlowlevelcomputercanrunoverhighlevelcomputerwithoutmodificationBackwardcompatibility：programforcurrentcomputercanrunoverfuturecomputerwithoutmodification1.2StructureandFunctionComputerisacomplexsystemMillionsofbasicelectroniccomponentsHowtodescribeacomputer?HierarchicAteachlevel,onlystructureandfunctionareconcernedforthedesignerCh.1–1.2Structure:

thewayinwhichcomponentsrelatetoeachother

Function

:

theoperationofindividualcomponentsaspartofthestructureTop-downapproachtodescribeCh.1–1.2Allcomputerfunctionsare:Dataprocessing

Datastorage

Datamovement

ControlCh.1–1.2AFunctionalviewofthecomputerDataMovementApparatusControlMechanismDataStorageFacilityDataProcessingFacilityCh.1–1.2Datamovemente.g.disktomemoryDataMovementApparatusControlMechanismDataStorageFacilityDataProcessingFacilityCh.1–1.2DataStorage

e.g.InternetdownloadtodiskDataMovementApparatusControlMechanismDataStorageFacilityDataProcessingFacilityCh.1–1.2DataProcessingfrom/tostoragee.g.PSapictureDataMovementApparatusControlMechanismDataStorageFacilityDataProcessingFacilityCh.1–1.2ProcessingfromstoragetoI/Oe.g.dealingbyATMDataMovementApparatusControlMechanismDataStorageFacilityDataProcessingFacilityCh.1–1.2StructureCh.1–1.2Structure-TopLevelComputerMainMemoryInputOutputSystemsInterconnectionPeripheralsCentralProcessingUnitComputerCommunicationlinesCh.1–1.2CPUComputerArithmeticandLogicUnitControlUnitInternalCPUInterconnectionRegistersCPUI/OMemorySystemBusCPUCh.1–1.2CUCPUControlMemoryControlUnitRegistersandDecodersSequencingLogicControlUnitALURegistersInternalBusControlUnitCh.1–1.2Whystudythiscourse?Insomedegree,itteacheshowweplaygameincostandperformance.Asadesigner,wecanprogramaprocessorthatisembeddedinsomereal-timeorlargersystem.VocabularyCentralProcessingUnit:中央处理单元/CPUMainmemory：主存I/Osubsystem输入/输出子系统Interconnection：互连Component：部件/组件Arithmeticandlogicunit：算术逻辑单元Register：寄存器Single-chipmicrocomputer：单片机Integratedcircuit：集成电路VocabularyArchitecture&organization：组成与系统结构Attribute：属性Programmer：程序员Instructionset：指令集Addressingmemory：可寻址内存Interface：接口Transparency：透明性Peripheral：外设VocabularyCompatibility：兼容性Reducedinstructionsetcomputer：精简指令集计算机/RISCShort-termdatastorage：短时数据存储Long-termdatastorage：长时数据存储Processor：处理器Parallelandpipeline：并行与流水Microprogram:微程序KeypointsWhatisthecomputerorganization&architecture?TransparencyWhatarecomputerfunctionsMaincomponentsinanormalcomputerMaincomponentsinCPUandCUComputerOrganization&ArchitectureChapter2

ComputerEvolutionandPerformance2.1ABriefHistoryofComputer4generationsfromcomputerbirth1950~59

Vacuumtube1960~68

Transistor1969~77

IntegratedCircuits1978~?Large-scaleintegration(LSI)andVery-large-scaleintegration(VLSI)Ch.2-2.1ComputerPre-history

CharlesBabbageAnalyticalEngineApplication–MathematicalTables(Astronomy)andNauticalTables(Navy)Background–AnycontinuousfunctioncanbeapproximatedbyapolynomialTechnology–mechanicalgears,Jacquard’sloom,simplecalculatorsCh.2-2.1Started1943andFinished1946.J.PresperEckert&JohnMauchlyUniversityofPennsylvaniaUseduntil1955Thefirstgeneral-purposecomputer：ENIACCanconditionalJumpandbeprogrammable,distinguisheditfromearlieronesUsedforcomputingartilleryfiringtablesCh.2-2.1ENIAC-detailsDecimal(notbinary)20accumulatorsof10digitsProgrammedmanuallybyswitches18,000vacuumtubes30tons15,000squarefeet140kWpowerconsumption5,000additionspersecondCh.2-2.1VonNeumann/TuringBegin1946,butnotcompleted1952Storedprogramconcept

Mainmemorystoringprogramsand

dataALUoperatingonbinarydataControlunitinterpretinginstructions

from

memoryandexecutingthemInputandoutputequipmentoperatedbycontrolunitPrincetonInstituteforAdvancedStudies–IASCh.2-2.1StructureoftheIAScomputerCh.2-2.1

IAS–details1000x40bitwords（100040bitstorageunits）Binarynumber2x20bitinstructions（8bitopcode，12bitaddress）21instructions:datamove,processing,storage

Setofregisters(storageinCPU)MemoryBufferRegister,MemoryAddressRegister,InstructionRegister,InstructionBufferRegister

ProgramCounter

Accumulator

MultiplierQuotient

ExpandedstructureofIAScomputerCh.2-2.1IAS:InstituteforAdvancedStudy(1952)Ch.2-2.1IASInstructionSet21InstructionsDataTransferUnconditionalBranchConditionalBranchArithmeticAddressModifyCh.2-2.1CommercialComputerLaterof1946,EckertandMauchlyestablishedthefirstcomputercompany--ElectronicControlCorp.TheirfirstsuccessfulmachinewastheUniversalAutomaticComputer(UNIVAC)I.UNIVACtasksinvolvescientificandcommercialapplications.Ch.2-2.1UNIVAC-1(1951)Ch.2-2.1IBM701(1953)Ch.2-2.12ndGeneration:TransistorComputerTransistorInventedin1947atBellLabsSmaller,CheaperandLessheatdissipationSolidstatedevicemadefromSiliconMorecomplexALUandControlUnitsUseofhigherlevellanguagesSystemSoftwareI/OChannelsNCR&RCAarefront-runnersIBM7000series(1952)DEC(PDP-1:firstDECcomputer)Ch.2-2.1IBM7094700seriesin1952lastmemberof7000in1964Memory2Kto32Kof36bitwordsMemoryCycletimefellfrom30microsecto1.4microsecNumberofOpcodesgrewfrom24to185UseofdatachannelsMultiplexortowhichallchannelsareconnectedCh.2-2.1IBM7090ConsoleCh.2-2.13rdgeneration:ICComputerUseofIntegratedCircuits(IC)SSI&MSIbasedcomputeristhe3rdcomputerExamplesIBMSystem/360andDECPDP-8FamilyconceptSimilaroridenticalinstructionsetSimilaroridenticaloperatingsystemIncreasingspeed,increasingnumberofI/Oports,IncreasingmemorysizeandIncreasingcostCh.2-2.1MicroelectronicsIn1958，revolutionizedachievementinelectronicscame:integratedcircuitwasinvented-TheeraofmicroelectronicsTransistor,resistance,capacitancemadefromsemiconductor，togetherwithwholecircuitcanbeputinasiliconwafer60slater,smallscaleintegrationandmediumscaleintegrationcameforthCh.2-2.1IntegratedCircuits(2007state-of-the-art)BareDiePrimarilyCrystallineSilicon1mm-25mmonaside2007featuresize~65nm=65x10-9m(then45,32,22,and16)100-1000Mtransistors25-100M“logicgates”3-10conductivelayers“CMOS”(complementarymetaloxidesemiconductor)-mostcommon.Ch.2-2.1ChipinPackagePrintedCircuitBoardsCeramicorplasticwithgoldwiresPackageprovides:spreadingofchip-levelsignalpathstoboard-levelheatdissipationfiberglassorceramic1-20conductivelayers1-20inonasideICpackagesaresoldereddown.Provides:MechanicalsupportDistributionofpowerandheatCh.2-2.1Moore’sLaw1965，GordonMoore-cofounderofIntelNumberoftransistorsonachipwilldoubleeveryyearSince1970’sdevelopmenthasslowedalittleNumberoftransistorsdoublesevery18monthsCostofachiphasremainedalmostunchangedHigherpackingdensitymeansshorterelectricalpaths,givinghigherperformanceSmallersizegivesincreasedflexibilityReducedpowerandcoolingrequirementsFewerinterconnectionsincreasesreliabilityCh.2-2.1Ch.2-2.1IBM360:AGeneral-PurposeRegister(GPR)MachineCh.2-2.1ProcessorState16General-Purpose32-bitRegistersmaybeusedasindexandbaseregisterRegister0hassomespecialproperties4FloatingPoint64-bitRegistersAProgramStatusWord(PSW)A32-bitmachinewith24-bitaddressesButnoinstructioncontainsa24-bitaddress!DataFormats8-bitbytes,16-bithalf-words,32-bitwords,64-bitdouble-wordsCh.2-2.1DECPDP-8(1965)FirstminicomputerDidnotneedairconditionedroomSmallenoughtositonalabbench$16,000-$100k+forIBM360Bus

structureCh.2-2.1DECPDP-8Ch.2-2.14G：LSI&VLSIComputer

Semiconductormemories64MBperchipMicroprocessorsInstructionset>150Addressbuswidth32DataBuswidth32Memoryaddressability4GBBusbandwidth32MB/secCachearchitecturesCh.2-2.1Intel4004DieIntroducedin1970Firstmicroprocessor2,250transistors12mm2108KHzCh.2-2.1Intel8086DieIntroducedin197929,0000transistors33mm25MHzBasicarchitectureoftheIA32PCCh.2-2.1Intel80486DieIntroducedin19891,200,000transistors81mm225MHz1stpipelinedimplementationofIA32PCCh.2-2.1PentiumDieIntroducedin19933,100,000transistors296mm260MHz1stsuperscalarimplementationofIA32Ch.2-2.1PentiumIII9,5000,000transistors125mm2450MHzIntroducedin1999SuperscalarprocessingCh.2-2.1IntelMicroprocessors1971-4004FirstmicroprocessorAllCPUcomponentsonasinglechip4bitFollowedin1972by80088bit1974–8080Intel’sfirstgeneralpurposemicroprocessor8086、8088、80286、80386、80486、pentium1、2、3、4Xeon(2001),Centrino,Itanium1,2,CoreCh.2-2.1SummaryonsingleCoreRISCRevolution

~1983,IBM801,UCBRISCproject,StanfordMIPSproject

-MakethemicroenginebetheCPU!

-Avoidinefficiencyofinterpretationlayer-Letcompilersdotheoptimizing-ImplementonsinglechipGenericUnixBoxCh.2-2.1SuperscalarProcessing~1990(IBMPower-1)topresent(almostallprocessorstoday)Basicidea:issuemultipleinstructionssimultaneously

-exploitfine-grainedparallelismwithintheinstructionstreamIn-order(Alpha21164)vs.out-of-order(MIPSR10K,PentiumPro)Aggressive,pipelinedcacheandmemorysubsystemsCh.2-2.1QuantityandUnitincommonuseBitByteK(Hz,bytes)：--1024＝210M:Mega(bytes,Hz)：--10242＝220G:Giga(bytes,Hz):--10243＝230T:tera(bytes，Hz):--10244＝240P:peta(bytes，Hz):--10245＝2502.2DesigningforPerformanceMicroprocessorspeedCPU/memorycapacityfollowsMoore’slaw

SeenextFig.ThetechniquesformeettheCPUspeedBranchpredicionDataflowanalysisSpeculativeexecutionMemoryspeedlagsofCPU’sspeed

CPUhastowaitBottleneckReducethewholeperformanceCh.2-2.2DRAMandProcessorCharacteristicsCh.2-2.2SolutionsOptimizesystemstructure,balancingthewholeperformanceofCPU,memoryandI/OImprovetheinterfacebetweenCPUandmemoryTheinterfaceisthekeypathresponsiblefortransferringinstructionanddata

IncreasenumberofbitsretrievedatonetimeMakeDRAM“wider”ratherthan“deeper”ChangeDRAMinterfaceCacheReducefrequencyofmemoryaccessMorecomplexcacheandcacheonchipIncreaseinterconnectionbandwidthHighspeedbusesHierarchyofbusesCh.2-2.2EvolutionofPentium8080：thefirstgeneralpurposeCPUintheworld8bit,19748086(8088)：16bit，Cache，1Mmainmemory；80286：extendedproductof808816Mmainmemory80386：32bit，multi-taskprocessor；80486：highperformanceCache，pipeline,mathcoprocessor;Pentium:Superscalar,instructionexecutedinparellel;Pentiumpro:branchprediction,dataflowanalysis,speculativeexecutionPⅡ：32bit.64bitinstructions：MMX；PⅢ：newfloatpointinstructions:128bit:SSE,support3-dgraphicsprocessingPⅣ：32bit.Providing128bitinstructions:SSE2Ch.2-2.2ClassificationofComputersSingle-chipSingle-boardMicrocomputerMinicomputerMediumcomputerLargecomputerSupercomputerCh.2-2.2RelationshipbetweensoftwareandhardwareCh.2-2.2SofthierarchiesofaComputerapplicationlanguage high-levellanguageassemblylanguageOS(jobcontrollanguage)machinelanguage(machineinstructionsystem)microprogram(microinstructionsystem)

topbottomCh.2-2.2VocabularyPipeliningandparallelexecution:流水与并行执行Speculativeexecution:推测执行Cache:快速缓存Decimal:十进制Binary:二进制Generalpurposecomputer:通用计算机VonNeumannMachine:冯-诺依曼计算机Opcode=operationcode:操作码Instructioncycle:指令周期Fetchcycle:取（读）周期VocabularyFlowchart:流程图Conditionbranch:条件转移Datatransfer:数据传送Upwardcompatible:向上兼容Multiplexor:复用器Bus:总线Magnetic-corememory:磁芯存储器Enduser:端用户Speechrecognition:语音识别Videoconferencing:视频会议VocabularyMultimediaauthoring:多媒体编著Workstation:工作站Client-server:客户机-服务器DRAM—dynamicrandomaccessmemory:动态随机存取存储器Branchprediction:转移预测Throughput:吞吐率Trade-off:折衷Supercomputer:超级计算机/巨型机Parallelism:并行性KeypointsWhatisthefirstcomputerintheworld?WhatfeaturesofvonNuemannmachineisthere?Howaboutitsstructure?Moorelaw?Typicalcomputerclassification?ComputerOrganization&ArchitectureChapter3

ATop-LevelViewOfComputerFunctionAndInterconnection3.1ComputercomponentsReviewThreekeyconceptsinvonNeumanarchitectureDataandinstructionarestoredinasingleread-writememoryThecontentsofthememoryareaddressedbylocationExecutionoccursinasequentialfashionCh.3-3.1Programminginhardwareandsoftware

Ch.3-3.1CPUCh.3-3.1MainComponentstheCentralProcessingUnit-CPUInput/outputI/OMainmemorySystembus3.2ComputerFunctionBasicfunctionofacomputerisexecutingprogram(asequenceofinstructions),tocompletespecialtasksCPUisacomponentofexecutinginstructionTheCPUtimeofprocessinganinstructioniscalledInstructionCycleAnexecutionofinstructioncanbesimplyviewedastwosteps:Fetchinstruction-Fetchcycleexecuteinstruction-ExecutecycleCh.3-3.2InstructionCycleFetchExecuteCh.3-3.2FetchCycleProcessorfetchesinstructionfrommemorylocationpointedtobyPCIncrementPCUnlesstoldotherwiseInstructionloadedintoInstructionRegister(IR)ProcessorinterpretsinstructionandperformsrequiredactionsCh.3-3.2OperationsinExecuteCycleProcessor-memorydatatransferbetweenCPUandmainmemoryProcessor-I/ODatatransferbetweenCPUandI/OmoduleDataprocessingSomearithmeticorlogicaloperationondataControlAlterationofsequenceofoperationse.g.jumpCombinationofaboveCh.3-3.21:load2:store5:addCh.3-3.2FlowofanInstructionInstructionaddresscalculationInstructionfetchInstructionoperationdecodingoperandaddresscalculationOperandfetchDataoperationOperandstorageCh.3-3.2Ch.3-3.2InterruptsDef.：amechanismallowingothermoduletobreakCPUexecutingsequence

TheobjectiveofinterruptstoimprovetheutilityoftheCPU

toallowCPUtoprocessurgenteventsCh.3-3.2Typesofinterruption

Programe.g.overflow,divisionbyzero，illegalinstruction，outside

referenceTimerGeneratedbyinternalprocessortimerUsedinpre-emptivemulti-tasking?I/OfromI/OcontrollerHardwarefailuree.g.memoryparityerrorCh.3-3.2Ch.3-3.2Ifinterruptispending,theprocessordoesthefollowing:SuspendexecutionofthecurrentprogrambeingexecutedandsaveitscontextSavecurrentcontextofPCandotherdataSetthePCtostartingaddressofaninterrupthandlerroutineTheuserprogramdoesnothavetocontainanyspecialcodetoaccommodateinterruptsTheprocessorandOSareresponsibleforsuspendingtheuserprogramandresumingitCh.3-3.2ProgramTiming:shortI/OwaitCh.3-3.2ProgramTiming:longI/OwaitCh.3-3.2AninterruptcycleisaddedtoinstructioncycleAfteran

instructioncycle,

processorchecksforinterrupt,IndicatedbyaninterruptsignalIfnointerrupt,fetchnextinstructionIfinterrupt:SuspendexecutionofcurrentprogramSavecontextSetPCtostartaddressofinterrupthandlerroutineProcessinterruptRestorecontextandcontinueinterruptedprogramCh.3-3.2Ch.3-3.2MultipleInterruptsDef.:aninterrupthandlerisinterruptedThemethodsofprocessingmultipleinterrupt:DisableinterruptsProcessorwillignorefurtherinterruptswhilstprocessingoneinterruptInterruptsremainpendingandarecheckedafterfirstinterrupthasbeenprocessedInterruptshandledinsequenceastheyoccurDefineprioritiesLowpriorityinterruptscanbeinterruptedbyhigherpriorityinterruptsWhenhigherpriorityinterrupthasbeenprocessed,processorreturnstopreviousinterruptCh.3-3.2Ch.3-3.2Ch.3-3.2Ch.3-3.2I/OfunctionExchangedatadirectlywiththeprocessorExchangedatadirectlywiththememory,insomecaseDirectmemoryaccess(DMA)-chapter73.3InterconnectionstructuresDef.:Thecollectionofpathsconnectingthevariousmodules

(a)MemoryCh.3-3.3(b)I/OmodulesPort:EachoftheinterfacetoanexternaldeviceGiveeachauniqueaddress(e.g.0,1,…,M-1)Ch.3-3.3(c)CPUCh.3-3.3Typesoftransfer:MemorytoprocessorProcessortomemoryI/OtoprocessorProcessortoI/OI/Otoorfrommemory-DMA3.4BusinterconnectionDef.:communicationpathsconnectingtwoormorecomponentsKeyfeatureofbus:providingsharedtransferringmediaOftengroupedAnumberofchannelsinonebus,e.g.32bitdatabusis32separatesinglebitchannelsBustypes:systembus,peripheralbusesSystemBus:busconnectingmaincomponentsofcomputerDataBus,AddressBus,ControlBusCh.3-3.4BusInterconnectionSchemeCh.3-3.4DatabusFunction:carrydataRememberthatthereisnodifferencebetween“data”and“instruction”atthislevelEachlinecancarryonly1bitatatimeBuswidth:thenumberoflinesBuswidthisakeyfactorindeterminingofsystemperformance8,16,32,64bitCh.3-3.4AddressbusFunction:

identifythesourceordestinationofdatae.g.CPUneedstoreadaninstruction(data)fromagivenlocationinmemoryBuswidthdeterminesmaximummemorycapacityofsysteme.g.8088has20bitaddressbusgiving1MaddressspaceCh.3-3.4ControlbusFunction:transfercontrolsignalsControluseofdataandaddressbus

Controlsignals:

command

andtiminginformationMemoryread/writesignalI/Oread/writeTransferACKBusRequestBusgrantInterruptrequest&ACKClocksignalsResetCh.3-3.4PhysicalstructureofbusWhatdobuseslooklike?ParallellinesoncircuitboardsRibboncablesStripconnectorsonmotherboardse.g.PCISetsofwiresCh.3-3.4Ch.3-3.4Multiple-busHierarchiesSingleBusProblemsLotsofdevicesononebusleadsto:Propagationdelays（bottleneck）Moredevicemeanmorelongbus,andthisleadsgreaterdelay.Longdatapathsmeanthatco-ordinationofbususecanadverselyaffectperformanceIfaggregatedatatransferapproachesbuscapacityMostsystemsusemultiplebusestoovercometheseproblemsCh.3-3.4TraditionalbusarchitectureCh.3-3.4High-performancebusCh.3-3.4ElementsofBusDesignType

BuswidthDedicated addressMultiplexed dataMethodofarbitration

DatatransfertypesCentralized readDistributed writeTiming

read-modify-writeSynchronousread-after-writeAsynchronousblockCh.3-3.4BusTypesDedicatedBus:

Multiplebuses,

e.g,Separatedata&addresslinesAdvantage:highthroughputDisadvantage:scaleandcostincreasesMultiplexedBus:

Sharedlines，timemultiplexingAddressvalidordatavalidcontrollineAdvantage-fewerlines，space,costDisadvantagesMorecomplexcontrolUltimateperformanceCh.3-3.4BusArbitrationMorethanonemoduleusingthebuse.g.CPUandDMAcontrollerOnlyonemodulemaycontrolbusatonetimeArbitrationmethod:centralised:abuscontroller/arbiter

isresponsibleforbususageandtime.AseparatemoduleorpartofCPU

DaisychainpollingCountertimingpollingSeparaterequestdistributed:nocentralizedcontroller,everymodulecontainsaaccesscontrollogic

Ch.3-3.4ChainpollingAdv.:scalableDisadv.:sensitivetocircuitfailureCh.3-3.4CounterpollingAdv.:flexiblepriority,insensitivetocircuitfailureDisadv.:complexcontrolCh.3-3.4SeparaterequestSeparateRequestAdv.:rapidresponse,flexiblepriorityDisadv.:toomanylines,complexcontrolCh.3-3.4CommunicationControlModesofBusCommunicationcontrol:addressinghowtostartandendtransmission,howtocoordinatemasterandslavemoduleAccordingtotiming,fourcommunicationmodescanusuallybeusedSynchronousAsynchronousHalf-synchronousSeparatedCh.3-3.4TimingDef.:thewayinwhicheventsarecoordinationonbusSynchronoustiming:theoccurrenceofeventsisdeterminedbyclocksignalsControlbusincludesclocklineAsingle1-0transmissionisabuscycleorbuscycleAlldevicescanreadclocklineUsuallysynconleadingedgeUsuallyasinglecycleforanevent???Asynchronoustiming:theoccurrenceofoneeventonabusfollowsanddependsontheoccurrenceofapreviouseventHalf-synchronousSeparateCommunicationCh.3-3.4SynchronousTimingDiagramAdv:simple,easytoimplementDisadv:inflexible,bottleneckCh.3-3.4AsynchronousTimingDiagramAdv:request-response,allowingfastandslowdevicesDisadv:controlcomplexCh.3-3.4TypesofAsynchronousCommunicationNon-interlockHalf-interlockFullinterlockCh.3-3.4Half-synchronousCommunicationClockisneededWaitlineisneededAllowingvariousspeedmodulestocommunicateharmoniouslyUsedforconnectinglowspeedandlargerspeeddifferencedevicesCh.3-3.4SeparateCommunicationBasicideais:Separatebuscycleintotwosub-cyclesInthefirstsub-cycle,masterputscommand,addressandotherinformationintothebus,thenabandonsthebusInthesecondsub-cycle,slavebeginstopreparedata(select,decode,load),thenappliesthebusandsendsthedataAdvantage:avoidingbusidlewaitingUsedforlargecomputerCh.3-3.4BuswidthThewidthofdatabus

hasan

impactonsystemperformanceThewidthofaddressbus

hasan

impactonsystem

capacityCh.3-3.4Datatransfertype3.5PCIPCI(PeripheralComponentInterconnection)：alsocalledhighspeedI/Obus

IntelreleasedtopublicCPU-independent,high-bandwidth,inexpensive64bit，264Mbps/4.2Gbps

CaninterconnecttootherbusesCentralizedcontrolandsyn.Timing,hiddenarbitrationCh.3-3.5Ch.3-3.5Supplement

ISA(industrialstandardarchitecture)Intel,16bit,alsocalledATbus,8MHz,16MB/sLowperformancebus,CPUparticipantEISA(extendedindustrialstandardarchitecture)ISACompatible,32bit8MHz,33MB/sVL-BUS:localbusstandardproposedbyvideoelectronicstandardassociationEvolvedfromCPUbus,33MHz,32bitHigh-performancebususedforCPUandhighspeeddevicesUSB(UniversalSerialBus)FlexiblefasterConnectorwithlowcostcableandhubVocabularyH