计算机组成教学课件：Chapter3 BasicInputOutput

Chapter3

BasicInput/OutputContentsAccessingI/ODevicesProgram-controlledI/OInterrupt-basedI/ODirectMemoryAccess2AccessingI/ODevicesComputersystemcomponentscommunicatethroughaninterconnectionnetwork.3AccessingI/ODevicesAddressspaceandmemoryaccessconceptsfromprecedingchapteralsoapplytoI/Odevices.EachI/Odevicemustconsistofsomeaddressablelocations.TheselocationsareaccessedwithLoadandStoreinstructions.TheselocationsareimplementedasI/Oregisters.4AccessingI/ODevicesTheI/OdevicesandthememorysharethesameaddressspaceMemory-mappedI/ONospecialcommandsforI/OI/Olooksjustlikememoryread/writeExample: Load R2,DATAIN Store R2,DATAOUTDATAINistheaddressofaregisterinaninputdevice.DATAOUTistheaddressofaregisterinanoutputdevice.5AccessingI/ODevicesMemory-mappedI/OAdvantageAnymachineinstructionthatcanaccessmemorycanbeusedtotransferdatatoorfromanI/Odevice.DisadvantageValuablememoryaddressspaceisusedup.6AccessingI/ODevicesSeparatedI/O(IsolatedI/O)SeparateaddressspacesSpecialI/OinstructionstoperformI/OtransfersE.g.,IN,OUTAdvantageI/OdevicesdealwithfewaddresslinesNoteAseparateI/OaddressspacedoesnotnecessarilymeanthattheI/Oaddresslinesarephysicallyseparatefromthememoryaddresslines.7I/ODeviceInterfaceInput/OutputDeviceProblemsWidevarietyofperipheralsDeliveringdifferentamountsofdataAtdifferentspeedsIndifferentformatsAllslowerthanCPUandRAMNeedI/Ointerfaces8I/ODeviceInterfaceAnI/Odeviceinterfaceisacircuitbetween

adeviceandtheinterconnectionnetwork.Providesthemeansfordatatransferand

exchangeofstatusandcontrolinformation.Includesdata,status,andcontrolregisters

accessiblewithLoadandStoreinstructions.Memory-mappedI/Oenablessoftwaretoviewtheseregistersaslocationsinmemory.91011Program-controlledI/O(Polling)Interrupt-drivenI/ODirectMemoryAccess(DMA) CommunicationMethodswithCPUProgram-ControlledI/ODiscussI/Oissuesusingkeyboard&display.Readkeyboardcharacters,storeinmemory,anddisplayonscreen.Implementthistaskwithaprogramthatperformsalloftherelevantfunctions.Thisapproachcalledprogram-controlledI/O.Howcanweensurecorrecttimingofactions

andsynchronizedtransfersbetweendevices?12SignalingProtocolforI/ODevicesAssumethattheI/Odeviceshaveawaytosenda“ready”signaltotheprocessor.Forkeyboard,indicatescharactercanberead

soprocessorusesLoadtoaccessdataregister.Fordisplay,indicatescharactercanbesentsoprocessorusesStoretoaccessdataregister.The“ready”signalineachcaseisastatusflag

instatusregisterthatispolledbyprocessor.13ExampleI/ORegistersForsampleI/Oprogramsthatfollow,assumespecificaddresses&bitpositionsforregisters.Registersare8bitsinwidthandword-aligned.Forexample,keyboardhasKINstatusflaginbitb1ofKBD_STATUSregisterataddress0x4004.ProcessorpollsKBD_STATUSregister,

checkingwhetherKINflagis0or1.IfKINis1,processorreadsKBD_DATAregister.1415WaitLoopforPollingI/OStatusProgram-controlledI/Oimplementedwithawaitloopforpollingkeyboardstatusregister:

READWAIT: LoadByte R4,KBD_STATUS

And R4,R4,#2

Branch_if_[R4]0 READWAIT

LoadByte R5,KBD_DATAKeyboardcircuitplacescharacterinKBD_DATAandsetsKINflaginKBD_STATUS.CircuitclearsKINflagwhenKBD_DATAisread.16WaitLoopforPollingI/OStatusSimilarwaitloopfordisplaydevice:

WRITEWAIT: LoadByte R4,DISP_STATUS

And R4,R4,#4

Branch_if_[R4]0 WRITEWAIT

StoreByte R5,DISP_DATADisplaycircuitsetsDOUTflaginDISP_STATUSafterpreviouscharacterhasbeendisplayed.CircuitautomaticallyclearsDOUTflag

whenacharacteristransferredtoDISP_DATA.17RISC-andCISC-styleI/OProgramsConsidercompleteprogramsthatusepollingtoread,store,anddisplayalineofcharacters.Eachkeyboardcharacterechoedtodisplay.Programfinisheswhencarriagereturn(CR)characterisenteredonkeyboard.LOCisaddressoffirstcharacterinstoredline.18RISC-styleprogram19CISC-styleprogramCISChasTestBit,CompareByteinstructionsaswellasauto-incrementaddressingmode20InterruptsDrawbackofawaitloop:processorisbusy.WithlongdelaybeforeI/Odeviceisready,cannotperformotherusefulcomputation.Insteadofusingawaitloop,letI/Odevicealerttheprocessorwhenitisready.Meanwhile,processorperformsotherusefultasksusingthewaitingperiod.2122InterruptAninterruptisaneventthatcausestheprocessortostopitscurrentprogramexecutionandswitchtoperforminganinterruptserviceroutine.InterruptRequestSignalAsignalthatanI/Odevicesendstotheprocessorthroughoneofthebuscontrollineswhenitisready.ConceptofInterrupt23ConceptofInterrupt24InterruptAcknowledgeSignalCPUissuesthesignaltotellthedevicethatinterrupthasbeenrecognized.Inresponse,deviceremovesinterruptrequest.Acknowledgementcanalsobedonebyaccessingstatusordataregisterindeviceinterface.InterruptServiceRoutine(InterruptHandler)Theroutineexecutedinresponsetoaninterruptrequestiscalledtheinterruptserviceroutine.ConceptofInterruptExampleofUsingInterruptsConsiderataskwithextensivecomputationandperiodicdisplayofcurrentresults.Timercircuitcanbeusedfordesiredinterval,withinterrupt-requestsignaltoprocessor.Twosoftwareroutines:COMPUTE&DISPLAY.ProcessorsuspendsCOMPUTEexecutiontoexecuteDISPLAYoninterrupt,thenreturns.DISPLAYisshort;timeismostlyinCOMPUTE.2526Interrupt-ServiceRoutineDISPLAYisaninterrupt-serviceroutine.Forexample,assumeinterruptsignalassertedwhenprocessorisexecutinginstructioni.Instructioncompletes,thenPC(i+1)savedtotemporarylocationbeforeexecutingDISPLAY.Return-from-interruptinstructioninDISPLAY

restoresPCwiththesavedaddressfromthattemporarystoragelocation.Savereturnaddressonstackorinaregister.Saving/restoringofgeneral-purposeregisterscanbeautomaticorprogram-controlled.2728DifferencebetweensubroutineandinterruptserviceroutineAsubroutineperformsafunctionrequiredbytheprogramfromwhichitiscalled.Theinterruptserviceroutineisexecutedatanytimeduetointerrupt,notduetoCall.Itmaynothaveanythingincommonwiththeprogrambeingexecutedatthetimetheinterruptisreceived.Interrupt-ServiceRoutineEnablingandDisablingInterruptsMustprocessoralwaysrespondimmediatelytointerruptrequestsfromI/Odevices?Sometaskscannottolerateinterruptlatency

andmustbecompletedwithoutinterruption.Needwaystoenableanddisableinterrupts,

bothinprocessorandindeviceinterfaces.Providesflexibilitytoprogrammers.UsecontrolbitsinprocessorandI/Oregisters.29EventSequenceforanInterruptProcessorstatus(PS)registerhasIEbit.ProgramsetsIEto1toenableinterrupts,andsetsIEto0toignoreinterrupts.Weshouldensurethatthesameorotherrequestsignaldoesnotleadtosuccessiveinterruptions.Whenaninterruptisrecognized,processorsavesprogramcounterandstatusregister(IE=1).IEbitclearedto0sothatsameorothersignaldoesnotcausefurtherinterruptions.Afteracknowledgingandservicinginterrupt,restoresavedstate,whichsetsIEto1again.30HandlingMultipleDevicesAnumberofdevicescapableofinitiatinginterruptsmaybeconnectedtotheprocessor.Whichdeviceisrequestingservice?Howistheappropriateserviceroutineexecuted?Shouldinterruptnestingbepermitted?Howaretwoormoresimultaneousrequestshandled?31Polling(NonvectoredInterrupt)32For1stquestion,polldevicestatusregisters,checkingifIRQbitforeachdeviceisset.For2ndquestion,calldevice-specificroutineforfirstsetIRQbitthatisencountered.VectoredInterruptsVectoredinterruptsreduceservicelatency;

noinstructionsexecutedtopollmanydevices.Letrequestingdeviceidentifyitselfdirectlybysendingasignalorabinarycodetotheprocessoroverthebus(typicallydatabus).Processorusestheinformationtofindtheaddressofcorrectroutineinaninterrupt-vectortable.Thestartingaddressoftheinterrupt-serviceroutineofadevicearecalledtheinterruptvector.Interruptvectortablecontainsthememoryaddressesofinterrupthandlers.33VectoredInterrupts34Tablelookupisperformedbyhardware.Interrupt-vectortableislocatedatfixedaddress,butroutinescanbelocatedanywhereinmemory.VectoredInterrupts35DaisyChainVectoredInterrupts36PriorityInterruptNestingServiceroutinesusuallyexecutetocompletion.Insomecases,allowtoacceptaninterruptfromaspecialdeviceduringtheexecutionofaninterrupt-serviceroutineforanotherdevice.ThisisinterruptnestingItcanbedonebyhavingserviceroutinessetIEbitto1Formorecontrol,usedifferentprioritylevels.Currentlevelheldinprocessorstatusregister.Acceptrequestsonlyfromhigher-leveldevices.37SimultaneousRequestsTwoormoredevicesrequestatthesametime.Arbitrationorpriorityresolutionisrequired.WithsoftwarepollingofI/Ostatusregisters,serviceorderdeterminedbypollingorder.Withvectoredinterrupts,hardwaremustselectonlyonedevicetoidentifyitself.Usearbitrationcircuitsthatenforcedesiredpriorityorfairnessacrossdifferentdevices.38ControllingI/ODeviceBehaviorProcessorIEbitsettingaffectsalldevices.Desirabletohaveamechanismtocontrolwhetheradeviceisallowedtointerrupttheprocessor.AnIEbitinthedevice’scontrolregister.Suchacontrolregisteralsoenablesselectingthedesiredmodeofoperationforthedevice.AccessregisterwithLoad/Storeinstructions.Forexampleinterfaces,settingKIEorDIEto1enablesinterruptsfromkeyboardordisplay.39ProcessorControlRegistersInadditiontoaprocessorstatus(PS)register,othercontrolregistersareoftenpresent.IPSregisteriswherePSisautomaticallysavedwhenaninterruptrequestisrecognized.IENABLEhasonebitperdevicetocontrolifrequestsfromthatsourcearerecognized.IPENDINGhasonebitperdevicetoindicateifinterruptrequesthasnotyetbeenserviced.4041AccessingControlRegistersUsespecialMoveinstructionsthattransfervaluestoandfromgeneral-purposeregisters.TransferpendinginterruptrequeststoR4:

MoveControl R4,IPENDINGTransfercurrentprocessorIEsettingtoR2:

MoveControl R2,PSTransferdesiredbitpatterninR3toIENABLE:

MoveControl IENABLE,R342ExamplesofInterruptProgramsUsekeyboardinterruptstoreadcharacters,butpollingwithinserviceroutinefordisplayIllustrateinitializationforinterruptprograms,includingdatavariablesandcontrolregistersShowsavingofregistersinserviceroutineConsiderRISC-styleandCISC-styleprogramsWeassumethatpredeterminedlocationILOC

isaddressof1stinstructioninserviceroutine43444546MultipleInterruptSourcesTouseinterruptsforbothkeyboard&display,callsubroutinesfromILOCserviceroutineServiceroutinereadsIPENDINGregisterCheckswhichdevicebit(s)is(are)set

todeterminewhichsubroutine(s)tocallServiceroutinemustsave/restoreLinkregisterAlsoneedseparatepointervariabletoindicate

outputcharacterfornextdisplayinterrupt4748ExceptionsAnexceptionisanyinterruptionofexecution.ThisincludesinterruptsforI/Otransfers.Buttherearealsoothertypesofexceptions.Recoveryfromerrors:detectdivisionbyzero,orinstructionwithaninvalidOPcode.Debugging:useoftracemode&breakpoints.Operatingsystem:softwareinterrupttoenter.ThelasttwocasesarediscussedinChapter4.49RecoveryfromErrorsAftersavingstate,serviceroutineisexecuted.Routinecanattempttorecover(ifpossible)

orinformuser,perhapsendingexecution.WithI/Ointerrupt,instructionbeingexecutedatthetimeofrequestisallowedtocomplete.Iftheinstructionisthecauseoftheexception,serviceroutinemustbeexecutedimmediately.Thus,returnaddressmayneedadjustment.5051DirectMemoryAccessInterruptdrivenandprogrammedI/OrequireactiveCPUinterventionTransferrateislimitedCPUistiedupinmanaginganI/OtransferSolution:DirectMemoryAccess(DMA)Usedforhigh-speedblocktransfersdirectlybetweenanexternaldeviceandthemainmemoryADMAcontrollerisprovided

totakeovercontrolofthesystemfromCPUDuringthetransfer,theCPUisnotinvolved52DMAOperationProgram-ControlledI/OinDMA53DMAOperationDMAcontrolsdatatransfer54DMAOperationI/OInterruptinDMA55DMAOperationTheCPU“prepares”theDMAoperationbytransferringinformationtoaDMAcontroller(DMAC)LocationofthedataonthedeviceLocationofthedatainmemorySizeoftheblocktotransferDirectionofthetransferModeoftransfer(burst,cyclesteal)Whenthedeviceisreadytotransferdata,theDMACtakescontrolofthesystembuses(DMACdealswithtransfer),andCPUcarriesonwithotherworkDMACsendsinterruptwhenfinished56DMAControllerAcomputersystemwithDMAcontrollerBR:BusRequestBG:BusGrant57DMAControllerFunctionofDMAControllerTakeovercontrolofthedatatransferbetweenthememoryandI/Odevices.Forwordstransferred,theDMAcontrollerProvidesthememoryaddressProvidesallthebussignalthatcontroldatatransferIncreasesthememoryaddressforsuccessivewordsKeepstrackofthenumberoftransfers58DMAControllerRegistersinaDMAinterfaceStartingaddressWordcountDoneIEIRQStatusandcontrolWR/31301059DMAControllerInternalOrganization60DMATransferModeBurstMode(BlockMode)OncetheDMAcontrollerisgrantedaccesstothesystembusbytheprocessor,ittransfersallbytesofdatainthedatablockbeforerelinquishingcontrolofthesystembusbacktotheprocessor.UsageItisusefulforloadingprogramsordatafilesintomemory.DisadvantageRendertheprocessorinactiveforrelativelylongperiodsoftime.LowCPUefficiency61DMATransferModeCycleStealingModeOncetheDMAcontrollerobtainsaccesstothesystembus,ittransferson