EDA技术及FPGA应用设计交通灯控制器

-.z.本科课程设计报告课程名称：EDA技术与FPGA应用设计设计工程：交通灯控制器实验地点：CPLD实验室指导教师：*文爱2016年5月24日一、设计要求设计一个由一条主干道和一条支干道的十字路口的交通灯控制器，具体要求如下：(1)主、支干道各设有一个绿、黄、红指示灯，两个显示数码管。(2)主干道处于常允许通行状态，而支干道有车来才允许通行。当主干道允许通行亮绿灯时，支干道亮红灯。而支干道允许通行亮绿灯时，主干道亮红灯。(3)当主、支道均有车时，两者交替允许通行，主干道每次放行45s，支干道每次放行25s，由亮绿灯变成亮红灯转换时，先亮5s的黄灯作为过渡，并进展减计时显示。二、设计方案(1)设置支干道有车开关SB。(2)系统中要求有45秒、25秒和5秒三种定时信号，需要设计三种相应的计时显示电路。计时方法为倒计时。定时的起始信号由主控电路给出，定时时间完毕的信号输入到主控电路。(3)主控制电路的输入信号一方面来自车辆检测，另一方面来自45秒、25秒、5秒的定时到信号；输出有计时启动信号〔置计数起始值〕和红绿灯驱动信号。状态转移如下图，用状态机描述。三、设计步骤1.编写各个模块的VHDL程序。2.上机调试优化程序。3.程序合成器件模块，并连接原理图。4.编写并下载程序，进展硬件实现。四、模块构造五、模块源程序1.JTDKZLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYJTDKZISPORT(CLK,SB,t,RST:INSTD_LOGIC;en,MR,MY,MG,BR,BY,BG:OUTSTD_LOGIC;din:outSTD_LOGIC_vector(7downto0));ENDENTITYJTDKZ;ARCHITECTUREARTOFJTDKZISTYPESTATE_TYPEIS(A,B,C,D);SIGNALp_STATE,n_state:STATE_TYPE;BEGINreg:PROCESS(CLK，rst)ISBEGINifrst='1'thenp_STATE<=A;ELSIF(CLK'EVENTANDCLK='1')THENp_STATE<=n_state;ENDIF;endprocessreg;:PROCESS(sb,t,p_state)beginCASEp_STATEISWHENA=>MR<='0';MY<='0';MG<='1';BR<='1';BY<='0';BG<='0';IF(SBANDt)='1'THENn_STATE<=B;din<="00000101";EN<='0';ELSEn_STATE<=A;din<="01000101";EN<='1';ENDIF;WHENB=>MR<='0';MY<='1';MG<='0';BR<='1';BY<='0';BG<='0';IFt='1'THENn_STATE<=C;din<="00100101";EN<='0';ELSE n_STATE<=B;din<="01000101";EN<='1';ENDIF;WHENC=>MR<='1';MY<='0';MG<='0';BR<='0';BY<='0';BG<='1';IFt='1'THENn_STATE<=D;din<="00000101";EN<='0';ELSEn_STATE<=C;din<="01000101";EN<='1';ENDIF;WHEND=>MR<='1';MY<='0';MG<='0';BR<='0';BY<='1';BG<='0';IFt='1'THENn_STATE<=A;din<="01000101";EN<='0';ELSEn_STATE<=D;din<="01000101";EN<='1';ENDIF;ENDCASE;ENDPROCESS;ENDARCHITECTUREART;2.JSQLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYjsqISPORT(en,RST:INSTD_LOGIC;Din:INSTD_LOGIC_VECTOR(7DOWNTO0);CLK:INSTD_LOGIC;t:OUTSTD_LOGIC; QH,QL:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYjsq;ARCHITECTUREARTOFjsqISBEGINt<='1'WHEN(QH="0000"ANDQL="0000")ELSE'0';PROCESS(CLK,en,RST)BEGINIFRST='1'THENQH<="0100";QL<="0101";ELSIFCLK'EVENTANDCLK='1'THENIFen='0'THENQH<=Din(7DOWNTO4);QL<=Din(3DOWNTO0);elsIFQL=0THENQL<="1001";IFQH=0THENQH<="1001";ELSE QH<=QH-1;ENDIF;ELSEQL<=QL-1;ENDIF;ENDIF;ENDPROCESS;ENDARCHITECTUREART;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYwork1IS PORT(CLK:INSTD_LOGIC; RST:INSTD_LOGIC; ENA:INSTD_LOGIC; OUTY:OUTSTD_LOGIC_VECTOR(3DOWNTO0); COUT:OUTSTD_LOGIC); ENDwork1;ARCHITECTUREBEHAVOFwork1IS SIGNALCQI:STD_LOGIC_VECTOR(3DOWNTO0);BEGINP_REG:PROCESS(CLK,RST,ENA) BEGIN IFRST='1'THENCQI<="0000"; ELSIFCLK'EVENTANDCLK='1'THEN IFENA='1'THENCQI<=CQI+1; ENDIF; ENDIF; OUTY<=CQI; ENDPROCESSP_REG; COUT<=CQI(0)ANDCQI(1)ANDCQI(2)ANDCQI(3);ENDBEHAV;3.译码器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL; ENTITYwork1IS PORT(A:INSTD_LOGIC_VECTOR(3DOWNTO0); LED7S:OUTSTD_LOGIC_VECTOR(6DOWNTO0));END;ARCHITECTUREARTOFwork1ISBEGIN PROCESS(A) BEGIN CASEAIS WHEN"0000"=>LED7S<=NOT"0111111"; WHEN"0001"=>LED7S<=NOT"0000110"; WHEN"0010"=>LED7S<=NOT"1011011"; WHEN"0011"=>LED7S<=NOT"1001111"; WHEN"0100"=>LED7S<=NOT"1100110"; WHEN"0101"=>LED7S<=NOT"1101101"; WHEN"0110"=>LED7S<=NOT"1111101"; WHEN"0111"=>LED7S<=NOT"0000111"; WHEN"1000"=>LED7S<=NOT"1111111"; WHEN"1001"=>LED7S<=NOT"1101111"; WHEN"1010"=>LED7S<=NOT"1110111"; WHEN"1011"=>LED7S<=NOT"1111100"; WHEN"1100"=>LED7S<=NOT"0111001"; WHEN"1101"=>LED7S<=NOT"1011110"; WHEN"1110"=>L