基于fpga的交通灯控制设计

1FPGA示器用来显示允许通行或通行的时间倒计时。本设计我们是基于FPGA的采用大规模可编程逻辑器件FPGA，通过设计来实现译码显示模块6六部分组成。本设计在XilinxISE和 SE软件平台上使用VHDL语2显示的顺序为：左转 绿 黄 红灯15秒、80秒、45秒、5秒。状态表如表所表3- 红红红红绿黄55红绿黄红红红6六部分组成。各个模块的关系与构架如下图所示。1S的脉冲波。程序如下libraryuseuseieee.std_logic_unsigned.all;entityfenpinqi port(clk1khz:inclk1hz:outstd_logic); architectureaoffenpinqiisprocess(clk1khz) q:integer:=0; ifclk1khz'eventandclk1khz='1'thenifq=512thenr:=notr; elseendif;endif;endprocess;enda;controlcontrolclkSS的值来决定红绿灯的状程序如下libraryuseuseieee.std_logic_unsigned.all;entitycontrolisport(clk:ins:outstd_logic_vector(2downto0);loadat,loadbt:outstd_logic;at,bt:outstd_logic_vector(6downto0)); architectureaofcontrolsignalt:integerrange0to130:=0; clk'eventandclk='1'then then elsift=15then elsift=60thenelsift=65then elsift=80 s<="100";elsift=125 endendift=130then endif;endprocess;endclk，就进行一次减一操作。atdaojishi模块程序libraryuseuseieee.std_logic_unsigned.all;entityatdaojishiisport(clk,loadat:in std_logic_vector(6downto0); std_logic_vector(6downto0));endarchitectureaofatdaojishisignalcountat:std_logic_vector(6downto0);waituntilifloadat='1' elsecountat<=countat-1;endif;endprocess;endMainlibraryuseuseieee.std_logic_unsigned.all;entitymainisport s:instd_logic_vector(2downtolrgy:outstd_logic_vector(7downtoendarchitectureaofmainisvariableb:std_logic_vector(7downto0);caseswhen=>when=>when=>when=>when=>when => whenothers=>b:=" endcase;endprocess;end译码程序如下libraryuseuseieee.std_logic_unsigned.all;entityto8421bcdisport( std_logic_vector(3downto0); std_logic_vector(6downto0));endarchitectureaofto8421bcdis ifat>=" "then " " " " " " "endif;ifbt>=" "then " " " " " " "endif;endprocess;enda;libraryuseuseieee.std_logic_unsigned.all;entityyimaxianshiisport(at1,bt1:instd_logic_vector(3downto0);at2,bt2:instd_logic_vector(6downto0);aout1,aout2,bout1,bout2:outstd_logic_vector(7downto0));endyimaxianshi;architectureaofyimaxianshiiscaseat1when"0000"=> when"0001"=> when"0010"=> when"0011"=> when"0100"=> when"0101"=> when"0110"=> when"0111"=> when"1000"=> when"1001"=> others=>aout1<=" endcase;case when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>"; others=>aout2<=" endcase;case when"0000"=> when"0001"=> when"0010"=> when"0011"=> when"0100"=> when"0101"=> when"0110"=> when"0111"=> when"1000"=> when"1001"=> others=>bout1<=" endcase;casebt2when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>";when"=>"; others=>bout2<=" endcase;endprocess;enda;模块、yima模块和yimaxianshi模块。这些模块均经过设计、编译、仿真，结果正确。最后 测试和效果评估在分频器程序仿真结果图中，clk1khz1khz；clk1hz为输出脉1hz的信号。controlloadat，loadbtdaojishi模块测试（含两个clk，执行一次，并将结果输出。Mainmain模块程序仿真结果图中，S为输入信号，用来表明整个红绿灯的状态（6个状态：S0~S5）;lrgy为输出信号，代表整个红绿灯的亮和灭的情况，灯的排序从到低绿灯、黄灯，然后南北方向左转灯、红灯、绿灯、黄灯。从图中我们可以看出S的状态从”到“101aout1代表十位，aout2代表个位；bout1，bout2bt的值分解成个位和十bout1代表十位，bout2代表个位。仿真结果完全正确，符合预期。**Failure:(vsim-3807)Typesdonotmatchbetweencomponentandentityforport Time:0 tion: Instance:/abc_abc_sch_tb/uut/xlxi_2File:control.vhd#**Failure:(vsim-3807)Typesdonotmatchbetweencomponentandentityforport Time:0 tion: Instance:/abc_abc_sch_tb/uut/xlxi_2File:control.vhd#**Failure:(vsim-3807)Typesdonotmatchbetweencomponentandentityforport Time:0 tion: Instance:/abc_abc_sch_tb/uut/xlxi_2File:control.vhd 幻灯片文JPEG[1].