设计参考源码手册1746个zhcs464a

ZHCS464A–SEPTEMBER2011–REVISEDJANUARY 说 CSD87331Q3DNexFET™电源块是一款针对同步VIN3.3mmx3.3mm

3.3mm3.3mm的5V栅极驱动应用进行了优化，这个产品提供一个任一5V栅极驱动成对使用时，此解决方案能够提供(SON)封 俯视83836457(Pin12压降压调节器(VRD)应用

3.3mmx3.3mm

TYPICALPOWERBLOCK654321654321050EfficiencyPowerLossOutputCurrentPleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddierstheretoappearsattheendofthisdatasheet.Copyright©2011–2012,TexasInstrumentsNexFETCopyright©2011–2012,TexasInstrumentsPRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheInstrumentsstandardwarranty.Productionprocessingdoes EnglishDataSheet:necessarilyincludetestingofallThesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedevicecedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. UMTA=25°C(unlessotherwiseVoltageVINtoVVSWtoVVSWtoPGNDVTGtoVBGtoVPulsedCurrentRating,APowerDissipation,6WAvalancheEnergySyncFET,ID=42A,L=ControlFET,ID=24A,L=OperatingJunctionandStorageTemperatureRange,TJ,(1)StressesbeyondthoselistedunderAbsoluteumRatingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedisnotimplied.Exposuretoabsolute-um-ratedconditionsforextendedperiodsmayaffectdeviceMENDEDOPERATINGTA=25°(unlessotherwise GateDriveVoltage, VInputSupplyVoltage,VSwitchingFrequency,CBST=0.1µFOperatingAOperatingTemperature,POWERBLOCKTA=25°(unlessotherwise PowerLoss,PLOSSVIN=12V,VGS=5V,VOUT=1.3V,IOUT=10A,fSW=500kHz,LOUT=1µH,TJ=WVINQuiescentCurrent,TGtoTGR=0VBGtoPGND=Measurementmadewithsix10-µF(TDKC3216X5R1C106KTorequivalent)ceramiccapacitorscedacrossVNtoPGNDpinsandusingahighcurrent5VdriverIC.THERMALTA=25°C(unlessotherwiseTHERMAL ambient(Minambient(Maxcase(Topofcase(PGNDRθJCisdeterminedwiththedevicemountedona1-inch2(6.45-cm2),2oz.(0.071-mmthick)Cupadona1.5-inch×1.5-(3.81-cm×3.81-cm),0.06-inch(1.52-mm)thickFR4board.RθJCisspecifiedbydesignwhileRθJAisdeterminedbytheuser’sboardDevicemountedonFR4materialwith1-inch2(6.45-cm2)ELECTRICALTA=25°C(unlessotherwiseTESTQ1ControlQ2SyncStaticDraintoSourceVGS=0V,IDS=VVGS=0V,VDS=11VDS=0V,VGS=+10/VDS=VGS,IDS=1VEffectiveACOn-VIN=12V,VGS=5V,VOUT=1.3V,IOUT=10A,fSW=500kHz,LOUT=VDS=15V,IDS=SDynamic InputVGS=0V,VDS=f=Output79SeriesGateΩGateChargeTotalIDS=8AGateCharge-GatetoGateCharge-GatetoGateChargeatOutputVDS=14V,VGS=TurnOnDelayVDS=15V,VGS=4.5V,IDS=8A,RG=2ΩRiseTurnOffDelayFallDiode DiodeForwardIDS=8A,VGS= VReverseRecoveryVDS=14V,IF=di/dt=4ReverseRecoveryGHMaxRθJA= MaxRθJA=GHwhenmounted whenx1inch2(6.45cm2)of minimumpadareaxoz.(0.071-mm 2-oz.(0.071-mmIR0I IR0ITYPICALPOWERBLOCKDEVICETestConditions:VIN=12V,VDD=5V,fSW=500kHz,VOUT=1.3V,LOUT=1µH,IOUT=15A,TJ=125°C,unlessstated43PowerPowerLoss210

OutputCurrentFigure1.PowerLossvsOutput

PowerPowerLoss,1 JuncionTemperatureFigure2.PowerLossvsNatOutputNatOutputCurrentOutputCurrent AmbientTemperature

AmbientTemperatureFigure3.SafeOperatingArea–PCBVertical Figure4.SafeOperatingArea–PCBHorizontalOutputCurrentOutputCurrent BoardTemperatureFigure5.TypicalSafeOperating(1)TheTypicalPowerBlockSystemCharacteristiccurvesarebasedonmeasurementsmadeonaPCBdesignwithdimensionsof4.0”(W)×3.5”(L)×0.062”(H)and6copperlayersof1oz.copperthickness.SeeApplicationSectionfordetailedexnation.TYPICALPOWERBLOCKDEVICECHARACTERISTICS(TestConditions:VIN=12V,VDD=5V,fSW=500kHz,VOUT=1.3V,LOUT=1µH,IOUT=15A,TJ=125°C,unlessstatedPowerPowerLoss,1

1714

PowerPowerLoss,1

14SOASOATemperatureAdjSOATemperatureAdj2003505006508009501100SOATemperatureAdjSwitchingFrequency

InputVoltageFigure6.NormalizedPowerLossvsSwitching Figure7.NormalizedPowerLossvsInputPowerPowerLoss,1

2216110

PowerPowerLoss,1

16SOATemperatureSOATemperatureAdj0SOATemperatureAdj 3 SOATemperatureAdjOutputVoltage

00.7080.91OutputInductanceFigure8.NormalizedPowerLossvs.Output Figure9.NormalizedPowerLossvs.OutputTYPICALPOWERBLOCKMOSFETTA=25°C,unlessstatedVGS=VGS=8.0VVGS=4.5VVGS=IDS-Drain-to-SourceIDS-Drain-to-SourceCurrent-IDS-Drain-to-SourceCurrent- 0 VDS-Drain-to-SourceVoltage-Figure10.ControlMOSFET

VDS-Drain-to-SourceVoltage-Figure11.SyncMOSFETVDS=VDS=TC=125°CTC=25°CTC=−55°CIDS-Drain-to-SourceIDS-Drain-to-SourceCurrent-IDS-Drain-to-SourceCurrent- 0 0

VGS-Gate-to-SourceVoltage-

VGS-Gate-to-SourceVoltage-Figure12.ControlMOSFET Figure13.SyncMOSFETID=8AID=8AVGS-VGS-Gate-to-SourceVoltageVGS-Gate-to-SourceVoltage 0 Qg-GateCharge-nCFigure14.ControlMOSFETGate

0 Qg-GateCharge-nCFigure15.SyncMOSFETGateTYPICALPOWERBLOCKMOSFETCHARACTERISTICS(TA=25°C,unlessstatedCiss=CgdCiss=Cgd+CgsCoss=Cds+CgdCrss=Cgdf=1MHzVGS=C−CapacitanceC−Capacitance−C−Capacitance−0 0

VDS-Drain-to-SourceVoltage-

VDS-Drain-to-SourceVoltage-Figure16.ControlMOSFET Figure17.SyncMOSFETID=ID=VGSthVGSth-ThresholdVoltage-VGSth-ThresholdVoltage-

0

TC-CaseTemperature- TC-CaseTemperature-Figure18.ControlMOSFET Figure19.SyncMOSFETID=ID=TC=25°CTC=125ºC--RDSRDSon-On-RDSon-On- 0 VGS-Gate-to-SourceVoltage-Figure20.ControlMOSFETRDS(on)vs

VGS-Gate-to-SourceVoltage-Figure21.SyncMOSFETRDS(on)vsTYPICALPOWERBLOCKMOSFETCHARACTERISTICS(TA=25°C,unlessstatedNormalizedNormalizedOn-1

IDID=8ANormalizedNormalizedOn-1IDID=8A0

0

TC-CaseTemperature- TC-CaseTemperature-Figure22.ControlMOSFETNormalized Figure23.SyncMOSFETNormalizedTC=25°CTC=25°CISD−Source-to-DrainISD−Source-to-DrainCurrent-ISD−Source-to-DrainCurrent- 0 0

1

0

VSD−Source-to-DrainVoltage- VSD−Source-to-DrainVoltage-Figure24.ControlMOSFETBody Figure25.SyncMOSFETBodyTC=25°CTC=25°CIAV-PeakAvalancheCurrent-1

TC=25°CTC=25°CIAV-PeakAvalancheCurrent-1 tAV-TimeinAvalanche- tAV-TimeinAvalanche-Figure26.ControlMOSFETUnclampedInductive Figure27.SyncMOSFETUnclampedInductiveSwitchingAPPLICATIONEquivalentSystemManyoftoday’shighperformancecomputingsystemsrequirelowpowerconsumptioninanefforttoreducesystemoperatingtemperaturesandimproveoverallsystemefficiency.Thishascreatedamajoremphasisonimprovingtheconversionefficiencyoftoday’sSynchronousBuckTopology.Inparticular,therehasbeenanemphasisinimprovingtheperformanceofthecriticalPowerSemiconductorinthePowerStageofthisApplication(seeFigure28).Assuch,optimizationofthepowersemiconductorsintheseapplications,needstogobeyondsimplyreducingRDS(ON).FigureTheCSD87331Q3DispartofTI’sPowerBlockproductfamilywhichisahighlyoptimizedproductforuseinasynchronousbucktopologyrequiringhighcurrent,highefficiency,andhighfrequency.ItincorporatesTI’slatestgenerationsiliconwhichhasbeenoptimizedforswitchingperformance,aswellasminimizinglossesassociatedwithQGD,QGS,andQRR.Furthermore,TI’spatentedpackagingtechnologyhasminimizedlossesbynearlyeliminatingparasiticelementsbetweentheControlFETandSyncFETconnections(seeFigure29).AkeychallengesolvedbyTI’spatentedpackagingtechnologyisthesystemlevelimpactofCommonSourceInductance(CSI).CSIgreatlyimpedestheswitchingcharacteristicsofanyMOSFETwhichinturnincreasesswitchinglossesandreducessystemefficiency.Asaresult,theeffectsofCSIneedtobeconsideredduringtheMOSFETselectionprocess.Inaddition,standardMOSFETswitchinglossequationsusedtopredictsystemefficiencyneedtobemodifiedinordertoaccountfortheeffectsofCSI.FurtherdetailsbehindtheeffectsofCSIandmodificationofswitchinglossequationsareoutlinedinTI’sApplicationNoteSLPA009.FigureThecombinationofTI’slatestgenerationsiliconandoptimizedpackagingtechnologyhascreatedabenarkingsolutionthatoutperformsindustrystandardMOSFETchipsetsofsimilarRDS(ON)andMOSFETchipsetswithlowerRDS(ON).Figure30andFigure31comparetheefficiencyandpowerlossperformanceoftheCSD87331Q3DversusindustrystandardMOSFETchipsetscommonlyusedinthistypeofapplication.Thiscomparisonpurelyfocusesontheefficiencyandgeneratedlossofthepowersemiconductorsonly.TheperformanceofCSD87331Q3DclearlyhighlightstheimportanceofconsideringtheEffectiveACOn-Impedance(ZDS(ON))duringtheMOSFETselectionprocessofanynewdesign.SimplynormalizingtotraditionalMOSFETRDS(ON)specificationsisnotanindicatoroftheactualin-circuitperformancewhenusingTI’sPowerBlockPowerBlockHS/LSPowerBlockHS/LSRDSON=18m/6.7mDiscreteHS/LSRDSON=18m/6.7mDiscreteHS/LSRDSON=18m/5.5mVGS=5VVIN=12VVOUT=1.3VLOUT=fSW=500kHzTA=25ºC PowerLossPowerLossEfficiencyEfficiency OutputCurrentFigure

0 OutputCurrentFigureThechartbelowcomparesthetraditionalDCmeasuredRDS(ON)ofCSD87331Q3DversusitsZDS(ON).ThiscomparisontakesintoaccounttheimprovedefficiencyassociatedwithTI’spatentedpackagingtechnology.Assuch,whencomparingTI’sPowerBlockproductstoindividuallypackageddiscreteMOSFETsordualMOSFETsinastandardpackage,thein-circuitswitchingperformanceofthesolutionmustbeconsidered.Inthisexample,individuallypackageddiscreteMOSFETsordualMOSFETsinastandardpackagewouldneedtohaveDCmeasuredRDS(ON)valuesthatareequivalenttoCSD87331Q3D’sZDS(ON)valueinordertohavethesameefficiencyperformanceatfullload.Midtolight-loadefficiencywillstillbelowerwithindividuallypackageddiscreteMOSFETsordualMOSFETsinastandardpackage.ComparisonofRDS(ON)vs.EffectiveACOn-ImpedanceZDS(ON)(VGS=--DCMeasuredRDS(ON)(VGS=8TheCSD87331Q3DNexFET™powerblockisanoptimizeddesignforsynchronousbuckapplicationsusing5Vgatedrive.TheControlFETandSyncFETsiliconareparametricallytunedtoyieldthelowestpowerlossandhighestsystemefficiency.Asaresult,anewratingmethodisneededwhichistailoredtowardsamoresystemscentricenvironment.SystemlevelperformancecurvessuchasPowerLoss,SafeOperatingArea,andnormalizedgraphsallowengineerstopredicttheproductperformanceintheactualapplication.PowerLossMOSFETcentricparameterssuchasRDS(ON)andQgdareneededtoestimatethelossgeneratedbythedevices.Inanefforttosimplifythedesignprocessforengineers,TexasInstrumentshasprovidedmeasuredpowerlossperformancecurves.Figure1plotsthepowerlossoftheCSD87331Q3Dasafunctionofloadcurrent.ThiscurveismeasuredbyconfiguringandrunningtheCSD87331Q3Dasitwouldbeinthefinalapplication(seeFigure32).ThemeasuredpowerlossistheCSD87331Q3Dlossandconsistsofbothinputconversionlossandgatedriveloss.Equation1isusedtogeneratethepowerlosscurve.(VIN×IIN)+(VDD×IDD)–(VSW_AVG×IOUT)=Power ThepowerlosscurveinFigure1ismeasuredatthe mendedjunctiontemperaturesof125°Cunderisothermaltestconditions.SafeOperatingCurvesTheSOAcurvesintheCSD87331Q3Ddatasheetprovidesguidanceonthetemperatureboundarieswithinanoperatingsystembyincorporatingthethermalandsystempowerloss.Figure3toFigure5outlinethetemperatureandairflowconditionsrequiredforagivenloadcurrent.Theareaunderthecurvedictatesthesafeoperatingarea.AllthecurvesarebasedonmeasurementsmadeonaPCBdesignwithdimensionsof4”(W)×3.5”(L)×0.062”(T)and6copperlayersof1oz.copperNormalizedThenormalizedcurvesintheCSD87331Q3DdatasheetprovidesguidanceonthePowerLossandSOAadjustmentsbasedontheirapplicationspecificneeds.ThesecurvesshowhowthepowerlossandSOAboundarieswilladjustforagivensetofsystemsconditions.TheprimaryY-axisisthenormalizedchangeinpowerlossandthesecondaryY-axisisthechangeissystemtemperaturerequiredinordertocomplywiththeSOAcurve.ThechangeinpowerlossisamultiplierforthePowerLosscurveandthechangeintemperatureissubtractedfromtheSOAcurve.Figure32.TypicalCalculatingPowerLossandTheusercanestimateproductlossandSOAboundariesbyarithmeticmeans(seeDesignExample).ThoughthePowerLossandSOAcurvesinthisdatasheetaretakenforaspecificsetoftestconditions,thefollowingprocedurewilloutlinethestepstheusershouldtaketopredictproductperformanceforanysetofsystemDesignOperatingOutputCurrent=InputVoltage=OutputVoltage=SwitchingFrequency=Inductor=CalculatingPowerPowerLossat10A=1.8W(FigureNormalizedPowerLossforinputvoltage≈1.0(FigureNormalizedPowerLossforoutputvoltage≈0.95(FigureNormalizedPowerLossforswitchingfrequency≈1.15(FigureNormalizedPowerLossforoutputinductor≈1.04(FigureFinalcalculatedPowerLoss=1.8W×1.0×0.95×1.15×1.04≈CalculatingSOASOAadjustmentforinputvoltage≈0.1ºC(FigureSOAadjustmentforoutputvoltage≈-1.3ºC(FigureSOAadjustmentforswitchingfrequency≈4.2ºC(FigureSOAadjustmentforoutputinductor≈1ºC(FigureFinalcalculatedSOAadjustment=0.1+(–1.3)+4.2+1≈Inthedesignexampleabove,theestimatedpowerlossoftheCSD87331Q3Dwouldincreaseto2.05W.Inaddition,the umallowableboardand/orambienttemperaturewouldhavetodecreaseby4.8ºC.Figure33graphicallyshowshowtheSOAcurvewouldbeadjustedaccordingly.StartbydrawingahorizontallinefromtheapplicationcurrenttotheSOADrawaverticallinefromtheSOAcurveinterceptdowntotheboard/ambientAdjusttheSOAboard/ambienttemperaturebysubtractingthetemperatureadjustmentInthedesignexample,theSOAtemperatureadjustmentyieldsareductioninallowableboard/ambienttemperatureof4.8ºC.Intheeventtheadjustmentvalueisanegativenumber,subtractingthenegativenumberwouldyieldanincreaseinallowableboard/ambienttemperature.123123OutputCurrent Figure33.PowerBlockMENDEDPCBDESIGNTherearetwokeysystem-levelparametersthatcanbeaddressedwithaproperPCBdesign:ElectricalandThermalperformance.ProperlyoptimizingthePCBlayoutwillyield umperformanceinbothareas.Abriefdescriptiononhowtoaddresseachparameterisprovided.ElectricalThePowerBlockhastheabilitytoswitchvoltagesatratesgreaterthan10kV/µs.SpecialcaremustbethentakenwiththePCBlayoutdesignandcementoftheinputcapacitors,DriverIC,andoutputinductor.ThecementoftheinputcapacitorsrelativetothePowerBlock’sVINandPGNDpinsshouldhavethehighestpriorityduringthecomponentcementroutine.Itiscriticaltominimizethesenodelengths.Assuch,ceramicinputcapacitorsneedtobecedascloseaspossibletotheVINandPGNDpins(seeFigure34).TheexampleinFigure34uses6×10-µFceramiccapacitors(TDKPart#C3216X5R1C106KTorequivalent).Noticethereareceramiccapacitorsonbothsidesoftheboardwithanappropriateamountofviasinterconnectingbothlayers.IntermsofpriorityofcementnexttothePowerBlock,C5,C7,C19,andC8shouldfollowinorder.TheDriverICshouldbecedrelativelyclosetothePowerBlockGatepins.TGandBGshouldconnecttotheoutputsoftheDriverIC.TheTGRpinservesasthereturnpathofthehigh-sidegatedrivecircuitryandshouldbeconnectedtothePhasepinoftheIC(sometimescalledLX,LL,SW,PH,etc.).ThebootstrapcapacitorfortheDriverICwillalsoconnecttothispin.TheswitchingnodeoftheoutputinductorshouldbecedrelativelyclosetothePowerBlockVSWpins.MinimizingthenodelengthbetweenthesetwocomponentswillreducethePCBconductionlossesandactuallyreducetheswitchingnoiselevel.(1)Intheeventtheswitchnodewaveformexhibitsringingthatreachesundesirablelevels,theuseofaBoostResistororRCsnubbercanbeaneffectivewaytoeasilyreducethepeakringlevel.The mendedBoostResistorvaluewillrangebetween1.0Ohmsto4.7OhmsdependingontheoutputcharacteristicsofDriverICusedinconjunctionwiththePowerBlock.TheRCsnubbervaluescanrangefrom0.5Ohmsto2.2OhmsfortheRand330pFto2200pFfortheC.PleaserefertoTIAppNoteSLUP100formoredetailsonhowtoproperlytunetheRCsnubbervalues.TheRCsnubbershouldbecedascloseaspossibletotheVswnodeandPGNDseeFigure34(1)(1)KeongW.Kam,DavidPommerenke,“EMIysisMethodsforSynchronousBuckConverterEMIRootCauseysis”,UniversityofMissouri–RollaThermalThePowerBlockhastheabilitytoutilizetheGNDnesastheprimarythermalpath.Assuch,theuseofthermalviasisaneffectivewaytopullawayheatfromthedeviceandintothesystemboard.Concernsofsoldervoidsandmanufacturabilityproblemscanbeaddressedbytheuseofthreebasictacticstominimizetheamountofsolderattachthatwillwickdowntheviabarrel:IntentionallyspaceouttheviasfromeachothertoavoidaclusterofholesinagivenUsethesmallestdrillsizeallowedinyourdesign.TheexampleinFigure34usesviaswitha10mildrillholeanda16milcapturepad.Tenttheoppositesideoftheviawithsolder-Intheend,thenumberanddrillsizeofthethermalviasshouldalignwiththeenduser’sPCBdesignrulesandmanufacturingcapabilities.Figure mendedPCBLayout(TopMECHANICALQ3DPackageAALLb9dK43LLb9dK43563465Ee21781287TopEe21781287PinPinPinPinPinPinPinPinPin

Side

Bottomc ExposedtieclipsmayM0192AbcdEe0.6500.026Lθ–––K0.3000.01254Land 5481NOTE:Dimensionsareinmm81

0.550

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0.2000.3000.20054548181NOTE:Dimensionsareinmm

M0207 mendedcircuitlayoutforPCBdesigns,seeapplicationnoteSLPA005–ReducingRingingThroughPCBLayoutTechniques.Q3DTapeandReel1.754.00±0.10(SeeNote1.758.00

2.00ØØ12.00+030 –05.5012.00+030 –05.50NOTES:1.10-sphole-pitchcumulativetoleranceCambernottoexceed1mmin100mm,noncumulativeoverMaterial:blackstatic-dissipativeAlldimensionsareinmm,unlessotherwiseThickness:0.30MSL1260°C(IRandconvection)PbFreflowREVISION

ChangesfromOriginal(September2011)toRevision 添加的特性着重号：高达15A运 PACKAGEOPTIONPACKAGINGOrderableStatusPackagePackageEconMSLPeak8Pb-CU(1)ThemarketingstatusvaluesaredefinedasACTIVE:Product mendedfornewLIFEBUY:TIhasannouncedthatthedevicewillbedis,andalifetime-buyperiodisinNRND: mendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoes mendusingthispartinanewPREVIEW:Devicehasbeenannouncedbutisnotinproduction.SamplesmayormaynotbeOBSOLETE:TIhasdistheproductionofthe(2)Eco n-Thennedeco-friendlyclassification:Pb- (RoHS),Pb- (RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck informationandadditionalproductcontentdetails.TBD:ThePb-/Green nhasnotbeenPb-(RoHS):TI'sterms"Lead- "or"Pb-"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb- productsaresuitableforuseinspecifiedlead-processes.Pb-(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.Thecomponentisotherwiseconsider