DSP28335教程专业知识讲座

CommunicationsModule11TMS320C28x™MCUWorkshopCopyright©2023TexasInstruments.Allrightsreserved.

TechnicalTrainingOrganizationT

TO第1页LearningObjectivesSerialPeripheralInterface(SPI)SerialCommunicationInterface(SCI)MultichannelBufferedSerialPort(McBSP)Inter-IntegratedCircuit(I2C)EnhancedControllerAreaNetwork(eCAN)

Note:Upto1SPImodule(A),3SCImodules(A/B/C),2McBSPmodules(A/B),1I2Cmodule(A),and2eCANmodules(A/B)areavailableontheF2833xdevices.第2页Synchronousvs.AsynchronousSynchronousShortdistances(on-board)HighdatarateExplicitclockAsynchronouslongerdistancesLowerdatarate(

1/8ofSPI)Impliedclock(clk/datamixed)EconomicalwithreasonableperformanceC28xU2PCBPortC28xPCBPortDestination第3页LearningObjectivesSerialPeripheralInterface(SPI)SerialCommunicationInterface(SCI)MultichannelBufferedSerialPort(McBSP)Inter-IntegratedCircuit(I2C)EnhancedControllerAreaNetwork(eCAN)第4页SPIDataFlowSPIShiftRegisterSPIDevice#1-MasterSPIDevice#2-SlaveSimultaneoustransmitsandreceiveSPIMasterprovidestheclocksignalshiftshiftclockSPIShiftRegister第5页SPIBlockDiagramSPIRXBUF.15-0SPIDAT.15-0SPICLKSPISOMISPISIMOLSPCLKbaudrateclockpolarityclockphaseC28x-SPIMasterModeShownSPITXBUF.15-0LSBMSBTXFIFO_0TXFIFO_15RXFIFO_0RXFIFO_15第6页SPIDataCharacterJustificationProgrammabledatalengthof1to16bitsTransmitteddataoflessthan16bitsmustbeleftjustifiedMSBtransmittedfirstReceiveddataoflessthan16bitsarerightjustifiedUsersoftwaremustmask-offunusedMSB’s11001001XXXXXXXXXXXXXXXX11001001SPIDAT-Processor#1SPIDAT-Processor#2第7页SPIBaudRateRegister

SpixRegs.SPIBRR15-76-0reservedSPIBITRATESPICLKsignal=LSPCLK(SPIBRR+1)LSPCLK4, SPIBRR=3to127, SPIBRR=0,1,or2Needtosetthisonlywheninmastermode!第8页SelectSPIRegistersConfigurationControlSpixRegs.SPICCRReset,ClockPolarity,Loopback,CharacterLengthOperationControlSpixRegs.SPICTLOverrunInterruptEnable,ClockPhase,InterruptEnableMaster/SlaveTransmitenableStatusSpixRegs.SPISTRXOverrunFlag,InterruptFlag,TXBufferFullFlagFIFOTransmitSpixRegs.SPIFFTX FIFOReceiveSpixRegs.SPIFFRXFIFOEnable,FIFOResetFIFOOver-flowflag,Over-flowClearNumberofWordsinFIFO(FIFOStatus)FIFOInterruptEnable,InterruptStatus,InterruptClearFIFOInterruptLevel(NumberofWordsinFIFO)Note:refertothereferenceguideforacompletelistingofregisters第9页SPISummarySynchronousserialcommunicationsTwowiretransmitorreceive(halfduplex)Threewiretransmitandreceive(fullduplex)SoftwareconfigurableasmasterorslaveC28xprovidesclocksignalinmastermodeDatalengthprogrammablefrom1-16bits125differentprogrammablebaudrates第10页SerialPeripheralInterface(SPI)SerialCommunicationInterface(SCI)MultichannelBufferedSerialPort(McBSP)Inter-IntegratedCircuit(I2C)EnhancedControllerAreaNetwork(eCAN)LearningObjectives第11页SCIPinConnectionsTransmitter-databufferregisterSCIDevice#1SCIRXDSCITXDSCITXDSCIRXDSCIDevice#28Receiver-databufferregister8Transmitter-databufferregisterReceivershiftregisterTransmittershiftregister8Receiver-databufferregisterReceivershiftregisterTransmittershiftregister8(FullDuplexShown)RXFIFO_0RXFIFO_15RXFIFO_0RXFIFO_15TXFIFO_0TXFIFO_15TXFIFO_0TXFIFO_15第12页SCIDataFormatThisbitpresentonlyinAddress-bitmodeNRZ(non-returntozero)formatCommunicationsControlRegister(ScixRegs.SCICCR)0=1Stopbit1=2Stopbits0=Odd1=Even0=Disabled1=Enabled0=Disabled1=Enabled0=Idle-linemode1=Addr-bitmode#ofdatabits=(binary+1)e.g.110bgives7databitsStopBitsEven/OddParityParityEnableLoopbackEnableAddr/IdleModeSCIChar2SCIChar1SCIChar076543210StartLSB234567MSBAddr/DataParityStop1Stop2第13页SCIDataTimingStartBitLSBofDataMajorityVoteFallingEdgeDetected

Startbitvalidif4consecutiveSCICLKperiodsofzerobitsafterfallingedgeMajorityvotetakenon4th,5th,and6thSCICLKcyclesSCIRXDSCICLK(Internal)1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2Note:8SCICLKperiodsperdatabit第14页MultiprocessorWake-UpModesAllowsnumerousprocessorstobehookeduptothebus,buttransmissionoccursbetweenonlytwoofthemIdle-lineorAddress-bitmodesSequenceofOperation1.PotentialreceiverssetSLEEP=1,whichdisablesRXINTexceptwhenanaddressframeisreceived2.Alltransmissionsbeginwithanaddressframe3.IncomingaddressframetemporarilywakesupallSCIsonbus4.CPUscompareincomingSCIaddresstotheirSCIaddress5.Processfollowingdataframesonlyifaddressmatches第15页Idle-LineWake-UpModeIdletimeseparatesblocksofframesReceiverwakesupwhenSCIRXDhighfor10ormorebitperiodsTwotransmitaddressmethodsDeliberatesoftwaredelayof10ormorebitsSetTXWAKEbittoautomaticallyleaveexactly11idlebitsLastDataSTSPSTDataSCIRXD/SCITXDBlockofFramesSPSPLastDataSTAddrSPIdlePeriod10bitsorgreaterIdlePeriod10bitsorgreaterAddressframefollows10bitorgreateridle1stdataframeSPSTAddrIdleperiodsoflessthan10bits第16页Address-BitWake-UpModeAllframescontainanextraaddressbitReceiverwakesupwhenaddressbitdetectedAutomaticsettingofAddr/DatabitinframebysettingTXWAKE=1priortowritingaddresstoSCITXBUFLastDataSTSTDataSCIRXD/SCITXDBlockofFramesSPSPLastDataSTAddrSPIdlePeriodlengthofnosignificanceFirstframewithinblockisAddress.ADDR/DATAbitsetto11stdataframe0100SPSTAddr1SPnoadditionalidlebitsneededbeyondstopbits第17页SCIBaudRateRegistersBAUD15(MSB)BAUD14Baud-SelectMSbyteRegister(ScixRegs.SCIHBAUD)76543210BAUD13BAUD12BAUD11BAUD10BAUD9BAUD8BAUD6Baud-SelectLSbyteRegister(ScixRegs.SCILBAUD)76543210BAUD5BAUD4BAUD3BAUD2BAUD1BAUD7BAUD0(LSB)SCIbaudrate=LSPCLK(BRR+1)x8LSPCLK16,BRR=1to65535, BRR=0第18页SelectSCIRegistersControl1ScixRegs.SCICTL1Reset,Transmitter/ReceiverEnableTXWake-up,Sleep,RXErrorInterruptEnableControl2ScixRegs.SPICTL2TXBufferFull/EmptyFlag,TXReadyInterruptEnableRXBreakInterruptEnableReceiverStatusScixRegs.SCIRXSTErrorFlag,Ready,FlagBreak-DetectFlag,FramingErrorDetectFlag,ParityErrorFlag,RXWake-upDetectFlagFIFOTransmitScixRegs.SCIFFTX FIFOReceiveScixRegs.SCIFFRXFIFOEnable,FIFOResetFIFOOver-flowflag,Over-flowClearNumberofWordsinFIFO(FIFOStatus)FIFOInterruptEnable,InterruptStatus,InterruptClearFIFOInterruptLevel(NumberofWordsinFIFO)Note:refertothereferenceguideforacompletelistingofregisters第19页SCISummaryAsynchronouscommunicationsformat65,000+differentprogrammablebaudratesTwowake-upmultiprocessormodesIdle-linewake-up&Address-bitwake-upProgrammabledatawordformat1to8bitdatawordlength1or2stopbitseven/odd/noparityErrorDetectionFlagsParityerror;Framingerror;Overrunerror;BreakdetectionTransmitFIFOandreceiveFIFOIndividualinterruptsfortransmitandreceive第20页SerialPeripheralInterface(SPI)SerialCommunicationInterface(SCI)MultichannelBufferedSerialPort(McBSP)Inter-IntegratedCircuit(I2C)EnhancedControllerAreaNetwork(eCAN)LearningObjectives第21页McBSPBlockDiagram16DXR2TXBufferXSR216DXR1TXBufferXSR116DRR2RXBufferRBR2Register16DRR1RXBufferRBR1Register16RSR216RSR1MDXxMDRxMFSXxMFSRxMCLKXxMCLKRxPeripheral/DMABusPeripheral/DMABus16161616CPU第22页Definition:BitandWordCLKb7b6b5b4b3b2b1b0WordFSa1a0BitD“Word”or“channel”containsnumberofbits(8,12,16,20,24,32)“Bit”-onedatabitperserialclockperiod

第23页Definition:WordandFrame“Frame”-containsoneormultiplewordsw0w1w2w3w4w5w6w7FrameWordw6w7DFSNumberofwordsperframe:1-128第24页Multi-ChannelSelectionCh0-0Ch0-1Ch5-0Ch5-1Ch27-0Ch27-1Multi-channelmodecontrolledprimarilyviatworegisters:MCRMulti-channelControlReg(enablesMc-mode)R/XCER(A-H)Rec/XmtChannelEnableRegs(enable/disablechannels)Upto128channelscanbeenabled/disabledC

O

D

E

CM

c

B

S

PFrameTDMBitStreamCh0Ch1Ch31...0Ch0Ch1Ch31...1Transmit&ReceiveonlyselectedChannelsMulti-channelAllowsmultiplechannels(words)tobeindependentlyselectedfortransmit

andreceive(e.g.onlyenableCh0,5,27forreceive,thenprocessviaCPU)TheMcBSPkeepstimesyncwithallchannels,butonly“listens”or“talks”

ifthespecificchannelisenabled(reducesprocessing/busoverhead)第25页McBSPSummaryIndependentclockingandframingfortransmitandreceiveInternalorexternalclockandframesyncDatasizeof8,12,16,20,24,or32bitsTDMmode-upto128channelsUsedforT1/E1interfacing

-lawandA-lawcompandingSPImodeDirectInterfacetomanycodecsCanbeservicedbytheDMA第26页SerialPeripheralInterface(SPI)SerialCommunicationInterface(SCI)MultichannelBufferedSerialPort(McBSP)Inter-IntegratedCircuit(I2C)EnhancedControllerAreaNetwork(eCAN)LearningObjectives第27页Inter-IntegratedCircuit(I2C)PhilipsI2C-busspecificationcompliant,version2.1Datatransferratefrom10kbpsupto400kbpsEachdevicecanbeconsideredasaMasterorSlaveMasterinitiatesdatatransferandgeneratesclocksignalDeviceaddressedbyMasterisconsideredaSlaveMulti-MastermodesupportedStandardMode–sendexactlyndatavalues(specifiedinregister)RepeatMode–keepsendingdatavalues(usesoftwaretoinitiateastopornewstartcondition)28xxI2CI2CControllerI2CEPROM28xxI2C............Pull-upResistersVDDSerialData(SDA)SerialClock(SCL)第28页I2CBlockDiagramTXFIFORXFIFOI2CDXRI2CDRRI2CXSRI2CRSRClockCircuitsSDASCL第29页I2COperatingModesOperatingMode DescriptionSlave-receivermode Moduleisaslaveandreceivesdatafromamaster (allslavesbegininthismode)Slave-transmittermode Moduleisaslaveandtransmitsdatatoamaster (canonlybeenteredfromslave-receivermode)Master-receivermode Moduleisamasterandreceivesdatafromaslave (canonlybeenteredfrommaster-transmitmode)Master-transmittermodeModuleisamasterandtransmitstoaslave (allmastersbegininthismode)第30页I2CSerialDataFormatsSSlaveAddressR/WACKDataDataACKACKP1711n1n117-BitAddressingFormatS11110AAR/WACKAAAAAAAADataACKACKP171181n1110-BitAddressingFormatSDataACKDataDataACKACKP1n1n1n11FreeDataFormatR/W=0–masterwritesdatatoaddressedslaveR/W=1–masterreadsdatafromtheslaven=1to8bitsS=Start(high-to-lowtransitiononSDAwhileSCLishigh)P=Stop(low-to-hightransitiononSDAwhileSCLishigh)第31页I2CArbitrationArbitrationprocedureinvokediftwoormoremaster-transmitterssimultaneouslystarttransmissionProcedureusesdatapresentedonserialdatabus(SDA)bycompetingtransmittersFirstmaster-transmitterwhichdrivesSDAhighisoverruledbyanothermaster-transmitterthatdrivesSDAlowProceduregivesprioritytothedatastreamwiththelowestbinaryvalue10100101100101SCLSDADatafromdevice#1Datafromdevice#2Device#1lostarbitrationandswitchestoslave-receivermodeDevice#2drivesSDA第32页I2CSummaryCompliancewithPhilipsI2C-busspecification(version2.1)7-bitand10-bitaddressingmodesConfigurable1to8bitdatawordsDatatransferratefrom10kbpsupto400kbpsTransmitFIFOandreceiveFIFO第33页LearningObjectivesSerialPeripheralInterface(SPI)SerialCommunicationInterface(SCI)MultichannelBufferedSerialPort(McBSP)Inter-IntegratedCircuit(I2C)EnhancedControllerAreaNetwork(eCAN)第34页ControllerAreaNetwork(CAN)

AMulti-MasterSerialBusSystemCAN2.0BStandardHighspeed(upto1Mbps)Addanodewithoutdisturbingthebus(numberofnodesnotlimitedbyprotocol)Lesswires(lowercost,lessmaintenance,andmorereliable)Redundanterrorchecking(highreliability)Nonodeaddressing(messageidentifiers)BroadcastbasedsignalingCEDAB第35页CANBusCANNODEBCANNODEACANNODECCAN_HCAN_LTwowiredifferentialbus(usuallytwistedpair)Max.buslengthdependontransmissionrate40meters@1Mbps120W120W第36页CANNode

Wired-ANDBusConnectionRXTXCANController(e.g.TMS320F28335)CANTransceiver(e.g.TISN65HVD23x)CAN_LCAN_H120W120W第37页PrinciplesofOperationDatamessagestransmittedareidentifierbased,notaddressbasedContentofmessageislabeledbyanidentifierthatisuniquethroughoutthenetwork(e.g.rpm,temperature,position,pressure,etc.)AllnodesonnetworkreceivethemessageandeachperformsanacceptancetestontheidentifierIfmessageisrelevant,itisprocessed(received);otherwiseitisignoredUniqueidentifieralsodeterminesthepriorityofthemessage(lowerthenumericalvalueoftheidentifier,thehigherthepriority)Whentwoormorenodesattempttotransmitatthesametime,anon-destructivearbitrationtechniqueguaranteesmessagesaresentinorderofpriorityandnomessagesarelost第38页Non-DestructiveBitwiseArbitrationBusarbitrationresolvedviaarbitrationwithwired-ANDbusconnectionsDominatestate(logic0,busishigh)Recessiv