北邮数字电路综合实验报告

...wd......wd......wd...数字电路综合实验报告简易智能密码锁一、实验课题及任务要求设计并实现一个数字密码锁，密码锁有四位数字密码和一个确认开锁按键，密码输入正确，密码锁翻开，密码输入错误进展警示。根本要求：1、密码设置：通过键盘进展4位数字密码设定输入,在数码管上显示所输入数字。通过密码设置确定键〔BTN键〕进展锁定。2、开锁：在闭锁状态下，可以输入密码开锁，且每输入一位密码，在数码管上显示“-〞，提示已输入密码的位数。输入四位核对密码后，按“开锁〞键，假设密码正确则系统开锁，假设密码错误系统仍然处于闭锁状态，并用蜂鸣器或led闪烁报警。3、在开锁状态下，可以通过密码复位键〔BTN键〕来去除密码，恢复初始密码“0000〞。闭锁状态下不能去除密码。4、用点阵显示开锁和闭锁状态。提高要求：1、输入密码数字由右向左依次显示，即：每输入一数字显示在最右边的数码管上,同时将先前输入的所有数字向左移动一位。2、密码锁的密码位数〔4~6位〕可调。3、自拟其它功能。二、系统设计2.1系统总体框图2.2逻辑流程图2.3MDS图2.4分块说明程序主要分为6个模块：键盘模块，数码管模块，点阵模块，报警模块，防抖模块，控制模块。以下进展详细介绍。键盘模块本模块主要完成是4×4键盘扫描，然后获取其键值，并对其进展编码，从而进展按键的识别，并将相应的按键值进展显示。键盘扫描的实现过程如下：对于4×4键盘，通常连接为4行、4列，因此要识别按键，只需要知道是哪一行和哪一列即可，为了完成这一识别过程，我们的思想是，首先固定输出高电平，在读入输出的行值时，通常高电平会被低电平拉低，当当前位置为高电平“1〞时，没有按键按下，否则，如果读入的4行有一位为低电平，那么对应的该行肯定有一个按键按下，这样便可以获取到按键的行值。同理，获取列值也是如此，先输出4列为高电平，然后在输出4行为低电平，再读入列值，如果其中有哪一位为低电平，那么肯定对应的那一列有按键按下。由此可确定按键位置。X78按键储存键盘译码消抖9按键储存键盘译码消抖X456X123XX0键盘扫描x键盘扫描〔X为无效按键〕2.数码管模块本实验采用六位七段共阴极数码管，通过选通6个位选管脚，向相应的IO口送低电平来点亮其中任何一位数码管，因为现在采用四位密码锁，所以只是用了其中四个，最高位两位数码管位选全部置1.如下附上7段共阴极数码管真值表3.点阵模块点阵模块，共由8*8*2个发光二极管组成，行低电平有效，列高电平有效。要求在开锁模式和闭锁模式显示不同的图案，则先将要显示的每幅图像画8*8个小方格的矩形框中，再在有图案下落处的小方格里填上“1〞，无图案处填上“0〞，这样就形成了与图案所对应的二进制数据在该矩形框上的分布。当闭锁时以红色点阵显示，此时绿色点阵全部置0，反之亦然。4.报警模块当报警程序被调用，蜂鸣器输出高电平进展报警，表示输入密码错误5．防抖按键输入只有为15ms以上的高电平时才会读出按键值从而消除电路中的抖动。6.控制中心lockmode='1表示关锁，此时点阵显示落锁，按任何键都不会显示密码，清零或者开锁，在此时输入密码kwei从0开场不断加1，输入的密码位数在数码管上依次左移，当输入密码m与存放器中预设密码mm一样时，按下确认键btn2切换为开锁状态，lockmode=0，此时按下btn1表示清零，恢复为初始密码0000，按set键存放器内密码，按下btnloc切换为关锁状态。三、仿真波形分析在QUARTUS2中应用系统自带的功能进展波形仿真，这里采用了分模块仿真。主程序仿真在主要功能程序方面波形如下，在初始化模式按下set键系统进入修改密码状态，setmode波形显示高电平。为仿真方便，仅使kbin〔即行输入信号〕在1011和1111两个状态下相互转换，在不同的kbout〔即列扫描输出信号〕下分别对应4、5、6、7四个数字，故密码存放器m[x]为输入的修改后的密码。按下btn2〔确认键〕确认密码后，setmode变为低电平，即修改密码状态完毕。按下btn1时清零，密码存放器取值复原为0000，至此均为开锁状态下的操作，lockmode一直为低电平。按下闭锁键btnloc后，lockmode从0跳变到1，由此进入闭锁模式。按键消抖模块仿真当按下键时得到的高电平为输入x，持续一定时间前方可输出一个高电平，而无论按下的时间多长，都只输出一个高电平y，从而实现消除按键电路中的抖动。分频模块仿真为仿真方便，改变分频比。原程序在50Mhz时钟输入下，输出分别为1Mhz、 200hz、1000hz、500hz，分别用于键盘扫描、消抖模块输入、点阵扫描以及数码管扫描。数码管模块仿真由smgcatout输出可以看出低四位数码管依次选通。第i位选通时，smgzf为m[i]的七段数码管的译码值。点阵模块仿真当lockmode=1时dzcolr全部为0仅dzcolg显示图案；当lockmode=0时dzcolg全部为0由dzcolr显示图案；而dzrow一直在进展行扫描，形成了两种不同颜色点阵。报警模块仿真当bj=0时，fmq为0；bj=1时，fmq将clk分频后输出，即蜂鸣器发出声响。四、源程序-----------------------顶层文件-------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitylockisport(clk:instd_logic;setmode:outstd_logic;lockmode:outstd_logic;set:instd_logic;btn1,btn2,btnloc:instd_logic;smgzf:outstd_logic_vector(6downto0);smgcatout:outstd_logic_vector(5downto0);kbin:instd_logic_vector(3downto0);kbout:bufferstd_logic_vector(3downto0);dzrow,dzcolr,dzcolg:outstd_logic_vector(7downto0);fmq:outstd_logic);endlock;architecturebehaveoflockissignalsetm:std_logic;signallockm:std_logic;signallbj:std_logic;signallkwei:integerrange0to4;signallm1,lm2,lm3,lm4:integerrange0to9;signalclk_1:std_logic; --1MHz signalclk_2:std_logic; --200Hz signalclk_3:std_logic; --1000Hzsignalclk_4:std_logic;--500Hzcomponentkbis-----------键盘模块port(clk:instd_logic;set:instd_logic;btn1,btn2,btnloc:instd_logic;kbin:instd_logic_vector(3downto0);kbout:bufferstd_logic_vector(3downto0);bj:outstd_logic;setmod:outstd_logic;lockmod:outstd_logic;kbwei:outintegerrange0to4;m1x,m2x,m3x,m4x:outintegerrange0to9);endcomponent;componentsmgis-------------数码管显示模块port(clk:instd_logic;setmode:instd_logic;lockmode:instd_logic;kwei:inintegerrange0to4;m1,m2,m3,m4:inintegerrange0to9;smgzf:outstd_logic_vector(6downto0);smgcatout:outstd_logic_vector(5downto0));endcomponent;componentdzis-----点阵模块port(clk:instd_logic;--set:instd_logic;lockmode:instd_logic;dzrow,dzcolr,dzcolg:outstd_logic_vector(7downto0));endcomponent;componentalarmis------报警模块port(clk:instd_logic;bj:instd_logic;fmq:outstd_logic);endcomponent;componentfenpinis-------分频模块 port(clk:instd_logic; clk_out1:outstd_logic; clk_out2:outstd_logic; clk_out3:outstd_logic; clk_out4:outstd_logic); endcomponent;begina1:fenpinportmap(clk=>clk,clk_out1=>clk_1,clk_out2=>clk_2,clk_out3=>clk_3,clk_out4=>clk_4);u1:kbportmap(clk=>clk,set=>set,btn1=>btn1,btn2=>btn2,btnloc=>btnloc,kbin=>kbin,kbout=>kbout,bj=>lbj,setmod=>setm,lockmod=>lockm,kbwei=>lkwei,m1x=>lm1,m2x=>lm2,m3x=>lm3,m4x=>lm4);u2:smgportmap(clk=>clk_4,setmode=>setm,lockmode=>lockm,kwei=>lkwei,m1=>lm1,m2=>lm2,m3=>lm3,m4=>lm4,smgzf=>smgzf,smgcatout=>smgcatout);u3:dzportmap(clk=>clk_3,lockmode=>lockm,dzrow=>dzrow,dzcolr=>dzcolg,dzcolg=>dzcolr);u4:alarmportmap(clk=>clk,bj=>lbj,fmq=>fmq);setmode<=setm;lockmode<=lockm;end;-----------------------键盘模块-------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitykbisport(clk:instd_logic;set:instd_logic;btn1,btn2,btnloc:instd_logic;kbin:instd_logic_vector(3downto0);kbout:bufferstd_logic_vector(3downto0);bj:outstd_logic;setmod:outstd_logic;lockmod:outstd_logic;kbwei:outintegerrange0to4;m1x,m2x,m3x,m4x:outintegerrange0to9);endkb;architecturebehaveofkbissignaljpout:integerrange0to10;signalalarm:std_logic;signaltmp4:integerrange0to2499999;signalclkfd:std_logic;signalm1,m2,m3,m4,mm1,mm2,mm3,mm4:integerrange0to9;signalwei:integerrange0to3;signalkwei:integerrange0to4;signalsetmode:std_logic;signallockmode:std_logic;signalset1:std_logic;signalclear:std_logic;signalsure:std_logic;signallock:std_logic;signalen,finish:std_logic; signalbtn1_out,btn2_out,btnloc_out,set_out:std_logic; signalclk_1:std_logic; --1MHz signalclk_2:std_logic; --200Hz componentscanis port(clk_1:instd_logic; clk_2:instd_logic; row:instd_logic_vector(3downto0); col:bufferstd_logic_vector(3downto0); en_up:bufferstd_logic; y:outintegerrange0to10); endcomponent; componentfenpinis port(clk:instd_logic; clk_out1:outstd_logic; clk_out2:outstd_logic; clk_out3:outstd_logic; clk_out4:outstd_logic); endcomponent; componentdebounceis port(clk,x:instd_logic; y:outstd_logic); endcomponent;beginsetmod<=setmode;lockmod<=lockmode;bj<=alarm;kbwei<=kwei;m1x<=m1;m2x<=m2;m3x<=m3;m4x<=m4;u1:scanportmap(clk_1=>clk_1,clk_2=>clk_2,row=>kbin,col=>kbout,en_up=>en,y=>jpout);u2:fenpinportmap(clk=>clk,clk_out1=>clk_1,clk_out2=>clk_2,clk_out3=>open,clk_out4=>open);u3:debounceportmap(clk=>clk_2,x=>btn1,y=>btn1_out);u4:debounceportmap(clk=>clk_2,x=>btn2,y=>btn2_out);u5:debounceportmap(clk=>clk_2,x=>btnloc,y=>btnloc_out);u6:debounceportmap(clk=>clk_2,x=>set,y=>set_out);process(clk)beginif(clk'eventandclk='1')thenif(tmp4=2499999)thentmp4<=0;clkfd<=notclkfd;elsetmp4<=tmp4+1;endif;endif;endprocess;process(clk_1,en,jpout)beginif(clk_1'eventandclk_1='1')thenif(lockmode='1')then----------闭锁状态下输入密码并读入按键值后存入mmwei<=0;if(jpout/=10)thenif(kwei=3)thenmm4<=jpout;kwei<=kwei+1;elsif(kwei=2)thenmm3<=jpout;kwei<=kwei+1;elsif(kwei=1)thenmm2<=jpout;kwei<=kwei+1;elsif(kwei=0)thenmm1<=jpout;kwei<=kwei+1;endif;endif;if(sure='1')then---------确认后判断密码是否正确if((mm1=m1)and(mm2=m2)and(mm3=m3)and(mm4=m4))thenlockmode<='0';alarm<='0';----------正确开锁elsekwei<=0;alarm<='1';----------错误报警endif;endif;elsekwei<=0;---------------开锁状态下if(lock='1')then--------------上锁lockmode<='1';elseif(set1='1')thensetmode<='1';-------修改密码elsesetmode<='0';endif;if(clear='1')then-----------清零m1<=0;m2<=0;m3<=0;m4<=0;--mm1<=0;mm2<=0;mm3<=0;mm4<=0;wei<=0;kwei<=0;alarm<='0'elsif(setmode='1')thenif(jpout/=10)then----------------修改密码状态下读入按键值存入m并移位if(wei=0)thenm1<=m2;m2<=m3;m3<=m4;m4<=jpout;wei<=wei+1;elsif(wei=1)thenm1<=m2;m2<=m3;m3<=m4;m4<=jpout;wei<=wei+1;elsif(wei=2)thenm1<=m2;m2<=m3;m3<=m4;m4<=jpout;wei<=wei+1;elsif(wei=3)thenm1<=m2;m2<=m3;m3<=m4;m4<=jpout;wei<=0;endif;endif;if(sure='1')then-----------确认后完毕修改密码状态setmode<='0';alarm<='0';endif;endif;endif;endif;endif;endprocess;process(set,sure)--------修改密码键beginif(clkfd'eventandclkfd='1')thenif(set='1')thenset1<='1';endif;if(sure='1')thenset1<='0';endif;endif;endprocess;process(btn1)-----------清零键beginif(btn1='1')thenclear<='1';elseclear<='0';endif;endprocess;process(btn2)----------确认键beginif(btn2='1')thensure<='1';elsesure<='0';endif;endprocess;process(btnloc)-----闭锁键beginif(btnloc='1')thenlock<='1';elselock<='0';endif;endprocess;end;----------------------------键盘扫描-------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityscanis port( clk_1:instd_logic; --高频(forscan)1Mhzclkout1 clk_2:instd_logic; --低频(fordebounce)200hzclkout2 row:instd_logic_vector(3downto0); col:bufferstd_logic_vector(3downto0); en_up:outstd_logic; y:outintegerrange0to10 );endscan;architectureaofscanis signalen:std_logic; componentdebounceis port(clk,x:instd_logic; y:outstd_logic);endcomponent;begin u1:debounceportmap(clk=>clk_2,x=>en,y=>en_up); process(clk_1) begin if(clk_1'eventandclk_1='1')then---------列扫描 if(en='1')then col<="1000"; else casecolis when"1110"=>col<="1101"; when"1101"=>col<="1011"; when"1011"=>col<="1110"; whenothers=>col<="1110"; endcase; endif; endif; endprocess; process(clk_1,col,row) begin if(clk_1'eventandclk_1='1')then casecolis when"1000"=> if((row(3)androw(2)androw(1)androw(0))='1')then en<='0'; endif; when"1110"=> caserowis --when"1110"=>y<="1111"; when"1101"=>y<=1;en<='1';--1 when"1011"=>y<=4;en<='1';--4 when"0111"=>y<=7;en<='1';--7 whenothers=>y<=10; endcase; when"1101"=> caserowis when"1110"=>y<=0;en<='1';--0 when"1101"=>y<=2;en<='1';--2 when"1011"=>y<=5;en<='1';--5 when"0111"=>y<=8;en<='1';--8 whenothers=>y<=10; endcase; when"1011"=> caserowis --when"1110"=>y<="1111"; when"1101"=>y<=3;en<='1';--3 when"1011"=>y<=6;en<='1';--6 when"0111"=>y<=9;en<='1';--9 whenothers=>y<=10; endcase; whenothers=>null; endcase; endif; endprocess;enda;----------------------------消抖-------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydebounceis port( clk,x:instd_logic;-------------200hz低频时钟 y:outstd_logic );enddebounce;architectureaofdebounceis typestateis(s0,s1,s2,s3,s4);------------5个状态 signalpre_s,next_s:state;begin process(clk) begin if(clk'eventandclk='1')then pre_s<=next_s; endif; endprocess; process(pre_s,x)-------输入为连续3个或以上的高电平时，输出一个高电平 begin casepre_sis whens0=>-----------初始状态s0 if(x='1')then next_s<=s1; else next_s<=s0; endif; y<='0'; whens1=> if(x='1')then next_s<=s2; else next_s<=s0; endif; y<='0'; whens2=> if(x='1')then next_s<=s3; else next_s<=s0; endif; y<='0'; whens3=>------------连续3个高电平，输出一个高电平 y<='1'; next_s<=s4; whens4=>----------3个以上高电平，不再继续输出高电平 y<='0'; if(x='1')then next_s<=s4; else next_s<=s0; endif; endcase; endprocess;enda;---------------------------分频模块-------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfenpinis port( clk:instd_logic; clk_out1:outstd_logic; clk_out2:outstd_logic; clk_out3:outstd_logic; clk_out4:outstd_logic );endfenpin;architecturedivoffenpinis constantdiv1:integer:=24;--1Mhz，用于键盘扫描 constantdiv2:integer:=124999;--200hz，用于消抖 constantdiv3:integer:=24999;--1000hz，用于点阵扫描 constantdiv4:integer:=49999;--500hz，用于数码管扫描 signalc1:integerrange0todiv1; signalc2:integerrange0todiv2; signalc3:integerrange0todiv3; signalc4:integerrange0todiv4; signaltemp1:std_logic; signaltemp2:std_logic; signaltemp3:std_logic; signaltemp4:std_logic;beginprocess(clk) begin if(clk'eventandclk='1')then if(c1=div1)then temp1<=nottemp1; c1<=0; else c1<=c1+1; endif; if(c2=div2)then temp2<=nottemp2; c2<=0; else c2<=c2+1; endif; if(c3=div3)then temp3<=nottemp3; c3<=0; else c3<=c3+1; endif; if(c4=div4)then temp4<=nottemp4; c4<=0; else c4<=c4+1; endif; endif; endprocess; clk_out1<=temp1; clk_out2<=temp2; clk_out3<=temp3; clk_out4<=temp4;enddiv;------------------------------------数码管-------------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitysmgisport(clk:instd_logic;--500hzclkout4setmode:instd_logic;lockmode:instd_logic;kwei:inintegerrange0to4;m1,m2,m3,m4:inintegerrange0to9;----------四位密码的值smgzf:outstd_logic_vector(6downto0);---------编码值smgcatout:outstd_logic_vector(5downto0));endsmg;architecturebehaveofsmgissignalsmgcat:integerrange0to5;signalm1y,m2y,m3y,m4y:std_logic_vector(6downto0);beginprocess(clk)-----------位选码beginif(clk'eventandclk='1')thenif(smgcat=5)thensmgcat<=0;elsesmgcat<=smgcat+1;endif;endif;endprocess;process(setmode,lockmode,smgcat)beginif(lockmode='0')thencasesmgcatis--------------输入密码值在数码管显示，从左到右when0=>smgcatout<="110111";smgzf<=m1y;when1=>smgcatout<="111011";smgzf<=m2y;when2=>smgcatout<="111101";smgzf<=m3y;when3=>smgcatout<="111110";smgzf<=m4y;when4=>smgcatout<="111111";when5=>smgcatout<="111111";endcase;elsesmgzf<="0000001";--------------输入密码在数码管显示“-〞if(kwei=1)thensmgcatout<="111110";elsif(kwei=2)thensmgcatout<="111100";elsif(kwei=3)thensmgcatout<="111000";elsif(kwei=4)thensmgcatout<="110000";elsesmgcatout<="111111";endif;endif;endprocess;process(m1)--------------七段数码管真值表begincasem1iswhen0=>m1y<="1111110";when1=>m1y<="0110000";when2=>m1y<="1101101";when3=>m1y<="1111001";when4=>m1y<="0110011";when5=>m1y<="1011011";when6=>m1y<="1011111";when7=>m1y<="1110000";when8=>m1y<="1111111";when9=>m1y<="1111011";whenothers=>m1y<="0000000";endcase;endprocess;process(m2)begincasem2iswhen0=>m2y<="1111110";when1=>m2y<="0110000";when2=>m2y<="1101101";when3=>m2y<="1111001";when4=>m2y<="0110011";when5=>m2y<="1011011";when6=>m2y<="1011111";when7=>m2y<="1110000";when8=>m2y<="1111111";when9=>m2y<="1111011";whenothers=>m2y<="0000000";endcase;endprocess;process(m3)begincasem3iswhen0=>m3y<="1111110";when1=>m3y<="0110000";when2=>m3y<="1101101";when3=>m3y<="1111001";when4=>m3y<="0110011";when5=>m3y<="1011011";when6=>m3y<="1011111";when7=>m3y<="1110000";when8=>m3y<="1111111";when9=>m3y<="1111011";whenothers=>m3y<="0000000";endcase;endprocess;process(m4)begincasem4iswhen0=>m4y<="1111110";when1=>m4y<="0110000";when2=>m4y<="1101101";when3=>m4y<="1111001";when4=>m4y<="0110011";when5=>m4y<="1011011";when6=>m4y<="1011111";when7=>m4y<="1110000";when8=>m4y<="1111111";when9=>m4y<="1111011";whenothers=>m4y<="0000000";endcase;endprocess;end;------------------------点阵-------------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydzisport(clk:instd_logic;--1000hzclkout3lockmode:instd_logic;dzrow,dzcolr,dzcolg:outstd_logic_vector(7downto0));enddz;architecturebehaveofdzissignaldzcat:integerrange0to7;beginprocess(clk)----------------------------计数器输出dzcat用于行扫描beginif(clk'eventandclk='1')thenif(dzcat=7)thendzcat<=0;elsedzcat<=dzcat+1;endif;endif;endprocess;process(lockmode,clk)beginif(lockmode='1')then----------点阵显示闭锁图形casedzcatiswhen0=>dzrow<="01111111";dzcolr<="00000000";dzcolg<="00011000";when1=>dzrow<="10111111";dzcolr<="00000000";dzcolg<="00100100";when2=>dzrow<="11011111";dzcolr<="00000000";dzcolg<="00100100";when3=>dzrow<="11101111";dzcolr<="00000000";dzcolg<="01111110";when4=>dzrow<="11110111";dzcolr<="00000000";dzcolg<="01111110";when5=>dzrow<="11111011";dzcolr<="00000000";dzcolg<="01111110";when6=>dzrow<="11111101";dzcolr<="00000000";dzcolg<="01111110";when7=>dzrow<="11111110";dzcolr<="00000000";dzcolg<="00000000";endcase;else-----------------点阵显示开锁图形casedzcatiswhen0=>dzrow<="01111111";dzcolr<="00000110";dzcolg<="00000000";when1=>dzrow<="10111111";dzcolr<="00001001";dzcolg<="00000000";when2=>dzrow<="11011111";dzcolr<="00001001";dzcolg<="00000000";when3=>dzrow<="11101111";dzcolr<="11111100";dzcolg<="00000000";when4=>dzrow<="11110111";dzcolr<="11111100";dzcolg<="00000000";when5=>dzrow<="11111011";dzcolr<="11111100";dzcolg<="00000000";when6=>d