第八章综合与STA

第八章综合策略及静态时序分析OutlinesLogicSynthesis&CompilingStrategyPhysicalSynthesis&CompilingStrategySynthesisUsingSynopsys’sDesignCompiler(DC)StaticTimingAnalysis(STA)STAUsingSynopsys’sPrimetime(PT)StatisticalStaticTimingAnalysis(SSTA)WhatLogicSynthesisDo?Generatenetlistwithuserspecifiedlibrary(translate&mapping)Massagenetlisttomeetreleasecriteria(optimization)SelectingandUsingaCompilingStrategyCompilingStrategy:

Top-downThetop-leveldesignandallitssubdesignarecompiledtogetherAdvantages:

OnlytoplevelconstraintsareneededBetterresultsduetooptimizationacrossentiredesignDisadvantagesLongcompiletimesIncrementalchangestothesub-blocksrequirecompletere-synthesisToollimitforhandle“large”designCompilingStrategy：

Bottom-upTheindividualsubdesignsarecompiledseparatelyYoumayneedtodoTime-budgetingattopleveltogetconstraintfileforeachsubdesignStartingfromthebottomofthehierarchyandproceedingupthroughthelevelsofthehierarchyuntilthetop-leveldesigniscompiledCompilingStrategy：

Bottom-up–cont.AdvantagesEasiertomanagethedesignbecauseofindividualscriptsGoodqualityresultsingeneralbecauseofflexibilityintargetingandoptimizingindividualblocksDisadvantagesTedioustoupdateandmaintainmultiplescriptsCriticalpathsseenatthetoplevelmaynotbecriticalatlowerlevelOptimizingDesignArchitecturaloptimizatione.g.SelectingDesignWareimplementationsLogic-LeveloptimizationStructuring--forreduceddesignareaFlattening--forspeedoptimizationGate-LeveloptimizationDelayoptimizationDesignrulefixingAreaoptimizationTimingcorrectionismosteffectivewithplacementinformationE.g.,PhysicalsynthesisLargeCircuitOptimizationProblemsRun-timebecomesintractableQualityofsolutiondropssharplySuggestion

Circuitpartition–usingbottom-upsynthesisstrategy“Timingbudget”synthesisstrategyTop-down(RTL-to-gate)togetthetimingbudgetforeachmodule,thendosynthesisoptimizationoneachmodule,followedbygate-to-gatesynthesisoptimizationfortheentiredesignPreserveClockandResetNetworksClocknetworksaretypicallydonebyClockTreeSynthesis(CTS),notbysynthesizeAsynchronousresetnetworksarealsotypicallytreatedasspecialnetworks,w/insertingappropriatebuffersPreserveclock&resetnetworkExample：Synopsys’sDesignCompliler,set_dont_touch_network<name>OutlinesLogicSynthesis&CompilingStrategyPhysicalSynthesis&CompilingStrategySynthesisUsingSynopsys’sDesignCompiler(DC)StaticTimingAnalysis(STA)STAUsingSynopsys’sPrimetime(PT)StatisticalStaticTimingAnalysis(SSTA)WireDelayandDeviceDelayChallengeforLogicSynthesisToolForprocess0.18umorless,wiredelaylargerthandevicedelayWiresareclosertogetherWiresarenarrowerStatisticalwireloadmodel(set_wire_load)nolongerworksPhysicalViewLogicalViewPhysicalSynthesisPhysicalsynthesiscombinesSynthesis,PlacementandStatictiminganalysiswithrouteestimationtogetherItdoesnotusewireload-modelsThedelayiscalculatedbasedonplacementratherthanfanoutBenefitsFrontenddesignerscanconsiderphysicaleffectsearlierinthedesignprocessBettersynthesisresultsleadfastertimingclosurePhysicalConstraintsPhysicalsynthesisrequirestheconstraints:Physicalsizeofthemacro/chipPinlocationsGroupinginformationPhysicalSynthesisFlowRTL-to-placed-gateflow

Intputs:RTL,floorplan,timingconstraint,libsetupfileCouldtakeextremelylongtime,especiallyforlargedesigngate-to-placed-gateflowInputs:gatelevelnetlist,floorplan,timingconstraint,libsetupfile

OptimizingexistinggatelevelnetlistaccordingtotheplacementRecommendedflowforfasttimingclosureOutlinesLogicSynthesis&CompilingStrategyPhysicalSynthesis&CompilingStrategySynthesisUsingSynopsys’sDesignCompiler

StaticTimingAnalysis(STA)STAUsingSynopsys’sPrimetimeStatisticalStaticTimingAnalysis(SSTA)SynopsysDCFlowSpecifyLibraries

Target_libraryThetechnologylibrarieswhichcontainstandardcellsthatDesignCompilermapstoduringoptimizationLink_library Alltechnologylibrarieswhichcontainhardmacros,standardcellsthatDesignCompilerusestoresolvecellreferencesSynthetic_library ADesignWarelibraryisacollectionofreusablecircuit-designbuildingblocks(component).Technologyindependent.Symbol_library Symbollibrariescontaindefinitionsofthegraphicsymbolsthatrepresentlibrarycellsinthedesignschematics.

DefiningDesignEnvironment

DefiningtheOperatingConditionsDefiningWireLoadModelsModelingtheSystemInterfaceDesignConstraints

Designruleconstraintsset_max_transitionset_max_fanoutset_max_capacitanceDesignoptimizationconstraintsset_input_delayset_output_delayset_max_areaHintsHighfanoutnets/equaldelaypathcanbeachievedinDC:set_min_delay,set_max_delayExample:data/addressbusesforexternalSDRAMinterfaceDefiningClockcreate_clock–name–period–waveform[get_ports]set_clock_latency(insertiondelay)set_clock_uncertainty(skew)set_clock_transition(transitiontime)create_generated_clockSpecifyingI/OTimingRequirementsInputDelay–Aninputdelayisthespecificationofanarrivaltimeatinputportrelativetoaclockedge.Outputdelay–Anoutputdelayrepresentsanexternaltimingpathfromanoutputporttoaregister.

set_input_delay4.5–clockPHl1IN1set_output_delay4.3–clockPHl1OUT1SpecialPathControlSet_false_pathToignoreaparticularpathfortimingoroptimizationSet_multicycle_pathToinformDCregardingthenumberofclkcyclesaparticularpathrequired.Defaultis1cyclepathSet_max_delay/set_min_delayDefinethemax/mindelayrequiredforaparticularpathFalsePathAfalsepathisthepathwhichisneversensitized/caredduetothelogicconfiguration,expecteddatasequence,oroperatingmode.ItwillnotbecheckedinSTAe.g.set_false_path–from<list>to<list>Multi-cyclePathAmulti-cyclepathisApathdesignedtotakemorethanoneclockcyclefromlaunchtocapturee.g.set_multicycle_path2–setup–fromA-toBRunDesignCompiler(dc)Suggesttohave3files:Startupfile.synopsys_dc.setupConstraintfilesconstraints.tclDCscriptsdc_script.tclCodingGuidelinesforSynthesisScriptsAllscriptsshouldbeginwithaheaderdescribingfile,purpose,author,revisionCommentsshouldbeusedextensivelyAllscriptsshouldbeunderrevisioncontrolNohard-codednumbers,datavalues,orfilenamesshouldbeburiedinthebodyofthescriptsNohard-codedpathsshouldappearinanyscriptsScriptsshouldbeassimpleastheycanbeandstillmeettheirobjectivesCommoncommandssuchasdefininglib,searchpathsshouldbeinasinglesetupfile,.synopsys_dc.setupRecommendationAlwaysreadthelogfiletofind“Warning”Alwaysuseanalyze&elaborateAlwaysuselinktomakesurenothingismissingAlwaysusecheck_designandcheck_timingandunderstandthewarningmessagesAlwaysstartwithadefaultcompileAlwayssavethedesignwiththe-hierarchyoptionAlwaysputconstraintsintoaseparatescriptfileandcallitfromyourmainscriptUse-syntax_check&-context_checkpriortorunningascriptforthefirsttimeFixallcombinatorialfeedbackloopsreportedbyDCExample–.synopsys_dc.setup(tclformat)

#/*.synopsys_dc.sretup*/#/*********************************************************/setsearch_path[contact$search_path[list“.”“/usr/golden/library/std_cells”]]settarget_library[listex25_worst.dbex25_best.db]setlink_library[list“*”,ex25_worst.dbex25_best.db]setsymbol_library[listex25.sdb]

define_name_rulesBORG–allowed“A-Za-z0-9”-first_restricted“_”\-last_restricted“_”-max_length30\-map[contact[list“\*cell\*””mycell”][list“*-return””myreturn”]]setbus_naming_style{%s[%d]}setverilogout_no_tritruesetverilogout_show_unconnected_pinstrue#/*ForDFT:definescanstyle******/settest_default_scan_stylemultiplexer_flip_flopExampleofcreate_clockcreate_clock-nameSYS_CLK-period9-waveform[list04][get_pinspll_clk]set_clock_uncertainty-setup0.5SYS_CLKset_clock_uncertainty-hold0.5SYS_CLKset_clock_latency4-min[get_clocksSYS_CLK]set_clock_latency4.5-max[get_clocksSYS_CLK]set_clock_transition0.5[get_clocksSYS_CLK]set_dont_touch_network[get_clocksSYS_CLK]Set_ideal_network[get_clocksSYS_CLK]Exampleofcreate_generatedclockForaclkfromadivider:create_generated_clock-divide_by2-source[get_pinspll_clk]-name48MCLK[get_pins{crc/crm_clkc_clkgen/usb_clk}]set_clock_uncertainty-setup0.548MCLKset_clock_uncertainty-hold0.548MCLKset_clock_latency4-min[get_clocks48MCLK]set_clock_latency4.5-max[get_clocks48MCLK]set_clock_transition0.5[get_clocks48MCLK]set_dont_touch_network[get_clocks48MCLK]Set_ideal_network[get_clocks48MCLK]Example-constraint.tcl

#/****************************************/#/*Clockspecificationanddesignconstraints*/create_clock–period33–waveform[list016.5]tckset_dont_touch_network[listtcktrst]set_ideal_network[listtcktrst]set_clock_latency2.0tckset_clock_uncertainty–setup3.0tckset_driveing_cell–lib_cellBUFF1X–pinZ[all_inputs]set_input_delay20.0–clocktck–max[all_inputs]set_output_delay10.0–clocktck–max[all_outputs]

set_max_area0Example-dc_script.tcl#/*Genericsynthesisscriptforsub-modules*/#/*********************************************************/#/*Definedesignname*/setactive_designtap_bypass#/*******************************************************/#/*DefineentryinVerilogformat*/analyze–formatverilog[format“%s%s”$active_design“.v”]elaborate$active_designcurrent_design$active_designlink#/****************************************/#/*Defineenvironment*/set_wire_loadSMALL–modetopset_operating_conditionsWORSTExample-dc_script.tcl–cont.#/*Compilewithscaninsertion*/set_fix_multiple_port_nets–buffer_constant–allcompile–scancheck_testcreate_test_patterns–sample10preview_scaninsert_scancheck_test#/*Clean-upandgeneratethenetlistinveriloganddbformats*/remove_unconnected_ports[find-hierarchycell“*”]change_names–h–rulesBROG

set_dont_touch[current_design]

write–hierarchy–output[format“%s%s”$active_design“.db”]write–formatverilog–hierarchy-output[format“%s%s”$active_design“.v”]CheckListoftheReportIsthereanyWarningorErrormessageinlogfile?Isthereanytimingviolation?Isthereanydesignviolation?Isthereanyportdirectlyconnectingtopowersuppliesinsteadofthrougha“tie1/0cell”?OutlinesLogicSynthesis&CompilingStrategyPhysicalSynthesis&CompilingStrategySynthesisUsingSynopsys’sDesignCompiler(DC)StaticTimingAnalysis(STA)STAUsingSynopsys’sPrimetime(PT)StatisticalStaticTimingAnalysis(SSTA)HowSTAWork?AdvancedAnalysis

Dynamicsimulationreliesonqualityandcoverageoftest-bench,testvectorsSTAismainlyforverifyingallpossible

pathsofgate-leveldesignfortimingStaticTimingAnalysisTechniqueStaticTimingAnalysisInputvectorpatternindependentEverysourceofdatalaunchischeckedatdestinationsorsinksDeterminestheworstpossibletimeaneventwilloccurAdvantage–Comprehensive,guaranteealltimingpathsareanalyzedDisadvantage–Howdoesdistinguishbetweenfunctional&non-functionalpathsWhatSTAtoAnalyze?TraverseallstatictimingpathsPathsbeginatsourcepinsPrimaryInputsPathsendatsinkpinsPrimaryOutputsWherevertimingcheckareperformedStorageelements(flip-flop,latch)Timingelements(clockgate)WhatSTAtoAnalyze?–cont.CalculatelatestandearliestpossibleswitchingtimesindesignDeterminethearrivaltimeofsignalsfortheworstcase(latestorearliest)ofallpossiblepathsComparecalculatedsignalarrivaltimeswithexpectedtimesat“endpoints”IttypicallyReports:Setup/holdtimeClockskewMaximumtransitionMaximumfanoutMaximumcapacitanceMaximumtransition……WhatSTAnottoAnalyze?ItdoesnotperformadelayanalysisbasedfunctionalsimulationItdoesnotconsiderthelogicfunctioningofthecircuitsItdoesnotsupportself-timedasynchronouslogicwherenoglobalclockisusedTypeofTimingPathExampleFromprimaryinputstoflip-flopsFromflip-floptoflip-flopFromflip-floptoprimaryoutputFromprimaryinputstoprimaryoutput

SomeBasicConceptsSetupTimeandHoldTimeforFFsSetupTime-Thelengthoftimethatdatamuststabilizebeforetheclocktransition.HoldTime-ThelengthoftimethatdatamustremainstableattheinputpinaftertheactiveclocktransitionRecoveryTimeRecoverytime-istheminimumlengthoftimethattheactivelowsetorresetsignalmustremainhighbeforetheactiveedgeoftheclocktoensurecorrectfunctioningofthecell.TimeSlackSlacksisusedtodescribehowmuchofthebudgetdidthelogicusedupSlack-theresultingmarginbetweenrequired&actualtimeofsignaltravelinginthepath.