南理工紫金学院eda实验二

EDA技术与应用实验报告实验名称：格雷码、二进制转换电路姓名：Aa学号：120403班级：12级电科时间：2014.11.10南京理工大学紫金学院电光系实验目的（四号+黑体）1）学习VHDL代码修改。2）利用when…else…并行语句描述4位格雷码/二进制码转换电路。3）利用generate并行语句描述n位格雷码/二进制码转换电路。4）利用实验箱验证所设计电路的正确性，要求将输入输出的数据用数码管显示。实验原理4位格雷码转换为二进制表达式为：n位格雷码转换为二进制表达式为：WHENELSE条件信号赋值语句目标信号<=表达式1when条件1else 表达式2when条件2else ...... 表达式n-1when条件n-1else 表达式n;GENERATE语句标号：for循环变量in离散范围generate 并行处理语句； endgenerate标号；实验内容实验的代码1：:libraryieee;useieee.std_logic_1161.all;entitygtob_1isport(g1,g2,g3,g4:instd_logic;b1,b2,b3,b4:bufferstd_logic);end;architecturerhiofgtob_1isbeginb4<=g4;b3<=b4xorg3;b2<=b3xorg2;b1<=b2xorg1;endrhi;实验的代码2libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitygtob_2isport(g:instd_logic_vector(3downto0);b:bufferstd_logic_vector(3downto0));endgtob_2;architecturerhgofgtob_2isbeginb<="0000"wheng<="0000"else"0001"wheng<="0001"else"0011"wheng<="0010"else"0010"wheng<="0011"else"0111"wheng<="0100"else"0110"wheng<="0101"else"0100"wheng<="0110"else"0101"wheng<="0111"else"1111"wheng<="1000"else"1110"wheng<="1001"else"1100"wheng<="1010"else"1101"wheng<="1011"else"1000"wheng<="1100"else"1001"wheng<="1101"else"1011"wheng<="1110"else"1010";--wheng<="0000"elseendrhg;实验代码3：libraryieee;useieee.std_logic_1164.all;entitygtob_3isport(g:instd_logic_vector(3downto0);b:outstd_logic_vector(3downto0));endgtob_3;architecturerhgofgtob_3isbeginprocess(g)begincasegiswhen"0000"=>b<="0000";when"0001"=>b<="0001";when"0011"=>b<="0010";when"0010"=>b<="0011";when"0111"=>b<="0100";when"0110"=>b<="0101";when"0100"=>b<="0110";when"0101"=>b<="0111";when"1111"=>b<="1000";when"1110"=>b<="1001";when"1100"=>b<="1010";when"1101"=>b<="1011";when"1000"=>b<="1100";when"1001"=>b<="1101";when"1011"=>b<="1110";when"1010"=>b<="1100";--wheng<="0000"elseendcase;endprocess;endrhg;实验代码4：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitygtob_4isgeneric(n:integer:=3);port(g:instd_logic_vector(ndownto0);b:bufferstd_logic_vector(ndownto0));endgtob_4;architectureregofgtob_4isbeginb(n)<=g(n);g1:foriin0ton-1generateb(i)<=g(i)xorb(i+1);endgenerateg1;endreg