4位加法器设计EDA实验

加法电路实验报告 实验任务1、建立新的工程，编写四位加法器的VHDL代码。2、编译、仿真并下载到DE2实验板测试，完成4位加法器的设计。实验内容1、4位串行进位加法器1）设计电路2）VHDL代码（设计中，先编写1位的加法，在此基础上构造4位加法）1位全加：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYf_adderISPORT(a,b,c0:INSTD_LOGIC; s,c1:OUTSTD_LOGIC);ENDENTITYf_adder;ARCHITECTUREoneOFf_adderISSIGNALabc:STD_LOGIC_VECTOR(2DOWNTO0);BEGINabc<=a&b&c0;PROCESS(abc)BEGIN CASEabcIS WHEN"000"=>S<='0';c1<='0'; WHEN"001"=>S<='1';c1<='0'; WHEN"010"=>S<='1';c1<='0'; WHEN"011"=>S<='0';c1<='1'; WHEN"100"=>S<='1';c1<='0'; WHEN"101"=>S<='0';c1<='1'; WHEN"110"=>S<='0';c1<='1'; WHEN"111"=>S<='1';c1<='1';WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;ENDARCHITECTUREone;4位加法：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYf_4adderIS PORT(A,B:INSTD_LOGIC_VECTOR(3DOWNTO0); S:OUTSTD_LOGIC_VECTOR(3DOWNTO0); cin:INSTD_LOGIC; cout:OUTSTD_LOGIC);ENDENTITYf_4adder;ARCHITECTUREoneOFf_4adderIS COMPONENTf_adder PORT(a,b,c0:INSTD_LOGIC; c1,s:OUTSTD_LOGIC); ENDCOMPONENT; SIGNALc2,c3,c4:STD_LOGIC; BEGIN u1:f_adderPORTMAP(a=>A(0),b=>B(0),c0=>cin,c1=>c2,s=>S(0)); u2:f_adderPORTMAP(a=>A(1),b=>B(1),c0=>c2,c1=>c3,s=>S(1)); u3:f_adderPORTMAP(a=>A(2),b=>B(2),c0=>c3,c1=>c4,s=>S(2)); u4:f_adderPORTMAP(a=>A(3),b=>B(3),c0=>c4,c1=>cout,s=>S(3)); ENDARCHITECTUREone;2、输入输出带锁存的4位加法器1）设计电路2）VHDL代码1位锁存器：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYrsIS PORT(clk:INBIT; r:INSTD_LOGIC; q:OUTSTD_LOGIC );ENDENTITYrs;ARCHITECTUREfh1OFrsIS BEGIN PROCESS(clk) BEGIN IFclk'EVENTANDclk='1'THEN q<=r; ENDIF; ENDPROCESS;ENDARCHITECTUREfh1;4位锁存器：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYrs_4IS PORT(R:INSTD_LOGIC_VECTOR(3DOWNTO0); Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0); CLK0:INBIT);ENDENTITYrs_4;ARCHITECTUREoneOFrs_4IS COMPONENTrs PORT(clk:INBIT; r:INSTD_LOGIC; q:OUTSTD_LOGIC); ENDCOMPONENT; SIGNALCLK1:BIT; BEGIN CLK1<=CLK0; u1:rsPORTMAP(clk=>CLK1,r=>R(0),q=>Q(0)); u2:rsPORTMAP(clk=>CLK1,r=>R(1),q=>Q(1)); u3:rsPORTMAP(clk=>CLK1,r=>R(2),q=>Q(2)); u4:rsPORTMAP(clk=>CLK1,r=>R(3),q=>Q(3)); ENDARCHITECTUREone;带锁存4位加法：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYadder_4IS PORT(X,Y:INSTD_LOGIC_VECTOR(3DOWNTO0); Z:OUTSTD_LOGIC_VECTOR(3DOWNTO0); Cin:INSTD_LOGIC; Cout:OUTSTD_LOGIC; CLK:INBIT);ENDENTITYadder_4;ARCHITECTUREoneOFadder_4IS COMPONENTf_4adder PORT(A,B:INSTD_LOGIC_VECTOR(3DOWNTO0); S:OUTSTD_LOGIC_VECTOR(3DOWNTO0); cin:INSTD_LOGIC; cout:OUTSTD_LOGIC); ENDCOMPONENT; COMPONENTrs_4 PORT(R:INSTD_LOGIC_VECTOR(3DOWNTO0); Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0); CLK0:INBIT); ENDCOMPONENT; COMPONENTrs PORT(clk:INBIT; r:INSTD_LOGIC; q:OUTSTD_LOGIC); ENDCOMPONENT; SIGNALP,T,N:STD_LOGIC_VECTOR(3DOWNTO0); SIGNALCLK2:BIT; SIGNALcout1:STD_LOGIC; BEGIN CLK2<=CLK; u1:rs_4PORTMAP(CLK0=>CLK2,R=>X,Q=>P); u2:rs_4PORTMAP(CLK0=>CLK2,R=>Y,Q=>T); u3:f_4adderPORTMAP(A=>P,B=>T,cin=>Cin,cout=>cout1,S=>N); u4:rs_4PORTMAP(CL