实验四 译码器

实验名称：组合逻辑VHDL设计----译码器班级：09通信1学号：09811106姓名：顾礼萍一、用WITH-SELECT语句实现2-4译码器1.实体框图2.程序设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDECODER24BISPORT(A1,A0:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYDECODER24B;ARCHITECTUREONEOFDECODER24BISSIGNALS:STD_LOGIC_VECTOR(1DOWNTO0);BEGINS<=A1&A0;WITHSSELECTY<="1110"WHEN"00","1101"WHEN"01","1011"WHEN"10","0111"WHEN"11","ZZZZ"WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形图4.仿真波形分析二、用WITH-SELECT语句实现带使能端的3-8译码器1.实体框图2.程序设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDECODER38BISPORT(A2,A1,A0:INSTD_LOGIC;S3,S2,S1:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYDECODER38B;ARCHITECTUREONEOFDECODER38BISSIGNALG:STD_LOGIC_VECTOR(4DOWNTO0);BEGING<=S1&(S2ANDS3)&A2&A1&A0;WITHGSELECTY<="11111110"WHEN"10000","11111101"WHEN"10001","11111011"WHEN"10010","11110111"WHEN"10011","11101111"WHEN"10100","11011111"WHEN"10101","10111111"WHEN"10110","01111111"WHEN"10111","ZZZZZZZZ"WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形图4.仿真波形分析三、用WITH-SELECT语句实现驱动共阳极数码管七段显示译码器1.实体框图2.程序设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDECODER7BISPORT(A:INSTD_LOGIC_VECTOR(3DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(6DOWNTO0)ENDENTITYDECODER7B;ARCHITECTUREONEOFDECODER7BISSIGNALS:STD_LOGIC_VECTOR(3DOWNTO0);BEGINS<=A3&A2&A1&A0;WITHSSELECTY<="1111111"WHEN"0000","1111001"WHEN"0001","0100100"WHEN"0010","0110000"WHEN"0011","0011001"WHEN"0100","0010010"WHEN"0101","0000010"WHEN"0110","1111000"WHEN"0111","0000000"WHEN"1000","0010000"WHEN"1001","ZZZZZZZ"WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形图4.仿真波形分析思考题设计共阴极七段显示译码器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDECODER7BISPORT(A:INSTD_LOGIC_VECTOR(3DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(6DOWNTO0)ENDENTITYDECODER7B;ARCHITECTUREONEOFDECODER7BISSIGNALS:STD_LOGIC_VECTOR(3DOWNTO0);BEGINS<=A3&A2&A1&A0;WITHSSELECTY<="0000000"WHEN"0000","0000110"WHEN"0001","1011011"WHEN"0010","1001111"WHEN"0011","1100110"WHEN"0100","1101101"WHEN"0101","1111101"WHEN"0110","0000111"WHEN"0111","1111111"WHEN"1000","1101111"WHEN"1001","ZZZZZZZ"WHENOTHERS;ENDARCHITECTUREONE;设计2进制变换为格雷码的码制变换译码器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYDECODDER7CISGENERIC(n:INTEGER:=4);PORT(NORM:INSTD_LOGIC_VECTOR(N-1DOWNTO0);GREY:OUTSTD_LOGIC_VECTOR(N-1DOWNTO0));ENDENTITYDECODDER7C;ARCHITECTUREONEOFDECODDER7CISSIGNALTEMP_NORMAL:STD_LOGIC_VECTOR(N-1DOWNTO0);SIGNALTEMP_GREY:STD_LOGIC_VECTOR(N-1DOWNTO0);BEGINPROCESS(NORM)BEGINTEMP_NORMAL<=NORM;TEMP_