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PageP01-CoverP02-BlockDiagramP03-NotesListP06-AlvisoHOST(1/5)P07-AlvisoDDR(2/5)P08-AlvisoPCI-E(3/5)P09-AlvisoPOWER(4/5)P10-AlvisoPOWER(5/5)P12-DDRI-P13-DDRDecouplingP14-ClockGeneratorP15-CRTConn.P16-VGA/LCDP17-P21-P22-DVI/TV_OutP23-PCMCIAENECB1410&CB714P24-PCMCIASOCKETP25-TI1394ATSB43AB21AP26-LANBCM5788MP27-LANMagnetic&RJ45/RJ11P28-Mimi-PCISlotP29-AC97P30-AudioLineinSwitchP31-AMP&PageP01-CoverP02-BlockDiagramP03-NotesListP06-AlvisoHOST(1/5)P07-AlvisoDDR(2/5)P08-AlvisoPCI-E(3/5)P09-AlvisoPOWER(4/5)P10-AlvisoPOWER(5/5)P12-DDRI-P13-DDRDecouplingP14-ClockGeneratorP15-CRTConn.P16-VGA/LCDP17-P21-P22-DVI/TV_OutP23-PCMCIAENECB1410&CB714P24-PCMCIASOCKETP25-TI1394ATSB43AB21AP26-LANBCM5788MP27-LANMagnetic&RJ45/RJ11P28-Mimi-PCISlotP29-AC97P30-AudioLineinSwitchP31-AMP&AudioJackP32-SuperIOSMC217P33-ENE-P34-MDC/BT/KBD/TPConn.P35-BIOS&I/OPort&SATAHDDP36-RJ11/LIDSwitch/Fan/FIRP37-USB2.0ConnP38-DockingConn.P39-PWR_OK/RTCP40-DCINTERFACEP41-P42-PWR-DCIN/PrechargeP44-PWR-BatterySelectP50-PWR-DunlinLA-2601SchematicsIntelDothan/AlvisoGM(PM)/DDR-1(DDR-2)/ICH6-//A-CompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D1CompalFileName:LA-400/533H_A#(3MV43/VGApageIntelAlvisoPCBGApage DDR- DDR-SO-DIMMBANK0,1,2,LCDSignalChannelDDR-1TwoChannelDDR-2pagePCI-EUSBconnxpageUSBRJ11pageIntelICH6-mBGA-USBBTpagePCIAudioALC250AC-AMP&AudiopagepageBCM5788MBCM4401pageMiniPCIpageENECB714page1394pagePATAHDDSATALPCpagepageRJ45pageSlotpagepagepagePowerOn/OffpageSMsCpageENEpageDC/DCInterfaceRTCpagepageInt.pageSerialParellelDOCKINGpagePowerCircuitpagePowerOKpageDOCKINGTouchPadCONN.CompalFileName:LA-400/533H_A#(3MV43/VGApageIntelAlvisoPCBGApage DDR- DDR-SO-DIMMBANK0,1,2,LCDSignalChannelDDR-1TwoChannelDDR-2pagePCI-EUSBconnxpageUSBRJ11pageIntelICH6-mBGA-USBBTpagePCIAudioALC250AC-AMP&AudiopagepageBCM5788MBCM4401pageMiniPCIpageENECB714page1394pagePATAHDDSATALPCpagepageRJ45pageSlotpagepagepagePowerOn/OffpageSMsCpageENEpageDC/DCInterfaceRTCpagepageInt.pageSerialParellelDOCKINGpagePowerCircuitpagePowerOKpageDOCKINGTouchPadCONN.pagepageCompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D2*RJ-11/*COMPOSITEVideo*LINEIN/*Print*DCpageCRT/TVIntelDothanpageClockGeneratorpageThermalSensorpageVoltageBoardID/SKUIDTableforADBOARDIDExternalPCI139420213PIRQEECSMBus1ECSMBus2SmartBattery0001011X1010000X1001110X1001011XICH6MSMBus(ICSDDR1010DDR1010CompalElectronics,SCHEMATIC,M/BLA-DocumentRevVoltageBoardID/SKUIDTableforADBOARDIDExternalPCI139420213PIRQEECSMBus1ECSMBus2SmartBattery0001011X1010000X1001110X1001011XICH6MSMBus(ICSDDR1010DDR1010CompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D3BoardPCB012345673.3V+/-Ra/100K+/-BoardRb/VAD_BIDVAD_BIDVAD_BID0000018.2K+/-0.2160.2500.289218K+/-0.4360.5030.538333K+/-0.7120.8190.875456K+/-1.0361.1851.2645100K+/-1.4531.6501.7596200K+/-1.9352.2002.34172.5003.3003.300PowerACorbatterypowerrailforpowerCorevoltagefor1.05Vswitchedpower1.25VswitchedpowerrailforDDR1.5Valwaysonpower1.5Vswitchedpower1.8Vswitchedpower2.5Vpowerrailfor2.5Vswitchedpower3.3Valwaysonpower3.3Vpower3.3Vswitchedpower5Valwaysonpower5Vswitchedpower5VswitchedpowerrailforModule12ValwaysonpowerRTCFullS1(PowerOnS3(SuspendtoS4(SuspendtoS5(Soft H_D#[0..63] <6>1@2121236 4<33,44> 5<33,44>A24#DATAGROUP<6><6><6>2222<14><14>HOST2H_PW2<6><6><6><6><6><6>H_DR<6><6>2CONTROL21<6><6> 21<6>2<6>2H_DINV#0H_DINV#1H_DINV#2H_DINV#32H_DSTBN#0H_DSTBN#1H_DSTBN#2H_DSTBN#3H_DSTBP#0H_DSTBP#1H_DSTBP#2H_DSTBP#3 H_D#[0..63] <6>1@2121236 4<33,44> 5<33,44>A24#DATAGROUP<6><6><6>2222<14><14>HOST2H_PW2<6><6><6><6><6><6>H_DR<6><6>2CONTROL21<6><6> 21<6>2<6>2H_DINV#0H_DINV#1H_DINV#2H_DINV#32H_DSTBN#0H_DSTBN#1H_DSTBN#2H_DSTBN#3H_DSTBP#0H_DSTBP#1H_DSTBP#2H_DSTBP#3<6><18><18><6>H_DPW<18>H_PW<6,18>H_A20M#H_FERR#H_IGNNE#H_INIT#H_INTRH_NMILEGACYH_STPCLK#H_SMI#<6,18>TYCO_1612365-SCHEMATIC,M/BLA-THERMDA&THERMDCTrace/Space=10/10DocumentRev¬P期四,十二月30,D42111@1@11@1@1111@1211+1+1+2+21.8VFORDOTHAN-12@22222221.5VFORDOTHAN-1211222222222POWER,22222222222222<48><48><48><48><48><48><48>222222221<14><14> 11111111111+TYCO_1612365-TYCO_1612365-2222222222212121212TRACECLOSELY@1211+1+1+2+21.8VFORDOTHAN-12@22222221.5VFORDOTHAN-1211222222222POWER,22222222222222<48><48><48><48><48><48><48>222222221<14><14> 11111111111+TYCO_1612365-TYCO_1612365-2222222222212121212TRACECLOSELYCPU<SCHEMATIC,M/BLA-COMP0,COMP2layout:Width18milsandSpace25milsCOMP1,COMP3layout:Space25milsDocumentRev¬P期四,十二月30,D52POWER,GROUNG,RESERVEDSIGNALSANDESR,9mMLCC08055m 1111111 1111111 1111111 1111111 1111111222 R84 H_RS#[0..2]<4>PM@12 <4>H_D#[0..63]PM@12HA3#<19><19><19><19>MCH_CLKSEL1<19><19><19><19><19><19><19><19><19><19><19><19><11><11><12><12><11><11><12><12><11><11><12><12><4><4><14><14>CFG[19:18]:internalpull-PM_BMBUSY#<11><11><12><12><4><4><4><4><4><4><4><4><4><4><4><4>H_THERMTRIP#VGATEPLT_RST#R427212<11>CLK_DREF_96M#CLK_DREF_96M<11><12><12>CLK_DREF_SSC#12EXT_TS#0112EXT_TS#11<4><4><4><4>H_DPW<4>H_DR<4><4><4><4><4><4><4><4>H_XRCOMPR5021H_XSCOMP H_RS#[0..2]<4>PM@12 <4>H_D#[0..63]PM@12HA3#<19><19><19><19>MCH_CLKSEL1<19><19><19><19><19><19><19><19><19><19><19><19><11><11><12><12><11><11><12><12><11><11><12><12><4><4><14><14>CFG[19:18]:internalpull-PM_BMBUSY#<11><11><12><12><4><4><4><4><4><4><4><4><4><4><4><4>H_THERMTRIP#VGATEPLT_RST#R427212<11>CLK_DREF_96M#CLK_DREF_96M<11><12><12>CLK_DREF_SSC#12EXT_TS#0112EXT_TS#11<4><4><4><4>H_DPW<4>H_DR<4><4><4><4><4><4><4><4>H_XRCOMPR5021H_XSCOMPR472R721H_YSCOMPR68H_XSWING12H_XRCOMP&H_YRCOMPTrace/Space10/20 <4,18>22H_XSW111CompalElectronics,222SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D6 1212121DDR 11frequencyselectLow=DMIx2High=DMIx4*Low=DDR-High=DDR- Low=DT/TransportableCPUHigh=MobileCPU*Low=ReverseHigh=Normal 00=01=XORModeEnabled10=AllZMode11=NormalOperation(Default)Low=DisabledHigh=Enabled*(VCCLow=1.05V(Default)(VTTLow=1.05V(Default)22CFG18R41CFG19R422@2@CFG0R40CFG5R413CFG6R407CFG7R408CFG9R404CFG12R409CFG13R412CFG16R417210K_0402_5%2@22@2@2@2@2@CFG[17:3]:internalpull-<11><11><11><11><12><12><12><12><11><12><11><12><11><12><11><11><11><11><12><12><12><12><11><12><11><12><11><12><11><11><12><12><11>DDR_A_W<12>DDR_B_WCompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D7DDRADDRSYSTEMMEMORY <16> <16>GM@2.2K_0402_5% <16> <16>13<16,33>GM@12<16><16><14><14><22><22><22>2121<15><15><15>21<15>21<15>21<15><15>12 DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z1212DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z1212DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z21212<16>DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z21212DVI@0.1U_0402_16V4Z2DVI@0.1U_0402_16V4Z1212DVI@0.1U_0402_16V4Z212C100DVI@0.1U_0402_16V4Z2<16><16><16><16>C1042DVI@DVI@0.1U_0402_16V4Z12C114122C116DVI@212<16><16><16>DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z121212DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z121212<16><16>DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z121212<16>DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z1212DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z1212<16><16><16>DVI@0.1U_0402_16V4Z12DVI@1 <16> <16>GM@2.2K_0402_5% <16> <16>13<16,33>GM@12<16><16><14><14><22><22><22>2121<15><15><15>21<15>21<15>21<15><15>12 DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z1212DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z1212DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z21212<16>DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z21212DVI@0.1U_0402_16V4Z2DVI@0.1U_0402_16V4Z1212DVI@0.1U_0402_16V4Z212C100DVI@0.1U_0402_16V4Z2<16><16><16><16>C1042DVI@DVI@0.1U_0402_16V4Z12C114122C116DVI@212<16><16><16>DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z121212DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z121212<16><16>DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z121212<16>DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z1212DVI@0.1U_0402_16V4ZDVI@0.1U_0402_16V4Z1212<16><16><16>DVI@0.1U_0402_16V4Z12DVI@12C101DVI@0.1U_0402_16V4Z2C105DVI@2DVI@0.1U_0402_16V4Z1212DVI@<16><16><16>GM@31GM@GM@SCHEMATIC,M/BLA-31DocumentGM@¬P期四,十二月30,D8DDGGSS1212222D2G11SPCI-EXPRESSR381R382R400 1V2121V211+2222222222222222VCCHV(Ball11111120.1U_0402_16V4Z224.7U_0805_10V4Z20.1U_0402_16V4Z24.7U_0805_10V4Z2VCCA_LVDS(BallVCCTX_LVDS(BallA27,A28,B28)VCCA_CRTDAC(Ball11111224.7U_0805_10V4Z220.1U_0402_16V4Z2F371VCC_SYNC(Ball2VCCD_TVDAC(Ball112111111+1V212222222AM1V212V21VCCD_LVDS(BallVCCDQ_TVDAC(Ball21+2222VCCA_TVBG(Ball12111122222+3GPLL2212212222U_1206_16V4Z_V12222U_1206_16V4Z_V1222SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D9 11111111122222211111111122222221111111111V2121V211+2222222222222222VCCHV(Ball11111120.1U_0402_16V4Z224.7U_0805_10V4Z20.1U_0402_16V4Z24.7U_0805_10V4Z2VCCA_LVDS(BallVCCTX_LVDS(BallA27,A28,B28)VCCA_CRTDAC(Ball11111224.7U_0805_10V4Z220.1U_0402_16V4Z2F371VCC_SYNC(Ball2VCCD_TVDAC(Ball112111111+1V212222222AM1V212V21VCCD_LVDS(BallVCCDQ_TVDAC(Ball21+2222VCCA_TVBG(Ball12111122222+3GPLL2212212222U_1206_16V4Z_V12222U_1206_16V4Z_V1222SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D9 1111111112222221111111112222222111111111+11111111 111111SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D <7><7>12<7><7>341156789<7>LayoutNote:PlacenearDIMMM_CLK_DDR0111112222211112222<6><7>11111111111112222222222222LayoutDDR_A_BS#1every2<7><7>DDR_A_WPlaceonecapcloseDDR_A_Wresistorsterminatedto<7><6>M_ODT0<6>12434312114343DDR_A_MA1 22 1214343DDR_CS0_DIMMA#11243432 11434322 124323443112<12,14,38>R692R693CompalElectronics,<12,14,38>SCHEMATIC,M/BLA-12JAE_MM50-200B1-<7><7>12<7><7>341156789<7>LayoutNote:PlacenearDIMMM_CLK_DDR0111112222211112222<6><7>11111111111112222222222222LayoutDDR_A_BS#1every2<7><7>DDR_A_WPlaceonecapcloseDDR_A_Wresistorsterminatedto<7><6>M_ODT0<6>12434312114343DDR_A_MA1 22 1214343DDR_CS0_DIMMA#11243432 11434322 124323443112<12,14,38>R692R693CompalElectronics,<12,14,38>SCHEMATIC,M/BLA-12JAE_MM50-200B1-DocumentRev¬P期四,十二月30,D 12 22LayoutPlacetheseresistorcloselyDIMM0,alltracelengthLayoutPlacetheseresistorcloselyDIMM0,alltracelength<750mil22<7><7>12<7><7>345611789<7>11111LayoutNote:PlacenearDIMMM_CLK_DDR3222221111122222<6>1111111111111<7>2222222222222LayoutNote:Placeoneclosetoevery2DDR_B_BS#1DDR_B_RAS#DDR_CS2_DIMMB#<7><7>DDR_B_WresistorsterminatedtoDDR_B_W<7><6>M_ODT2<6>M_CLK_DDR4CompalElectronics,<11,14,38><11,14,38>R695R69422SCHEMATIC,M/BLA-12JAE_MM50-200B1-DocumentRev¬P期四,十二月30,D <7><7>12<7><7>345611789<7>11111LayoutNote:PlacenearDIMMM_CLK_DDR3222221111122222<6>1111111111111<7>2222222222222LayoutNote:Placeoneclosetoevery2DDR_B_BS#1DDR_B_RAS#DDR_CS2_DIMMB#<7><7>DDR_B_WresistorsterminatedtoDDR_B_W<7><6>M_ODT2<6>M_CLK_DDR4CompalElectronics,<11,14,38><11,14,38>R695R69422SCHEMATIC,M/BLA-12JAE_MM50-200B1-DocumentRev¬P期四,十二月30,D LayoutPlacetheseresistorcloselyDIMM0,alltracelengthLayoutPlacetheseresistorcloselyDIMM0,alltracelength<750mil DDR_CS2_DIMMB# DDR_B_W 2DDR_B_MA5 2 2 3 DDR_CS3_DIMMB# 2222222222222222CompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D2+1+111111111122222222222222CompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D2+1+11111111111111DistributeascloseaspossibletoDDR-SODIMM.ClockKCFBM-L11-201209-11222222*12KCFBM-L11-201209-111222Table:ICS111172PM_STP_PCI#CLK_PCI2=1,PinarePEREQ#PM_STP_CPU#21212R124122CLK_MCH_BCLK12CLK_CPU1#1212CLK_MCH_BCLK#12R1342CLK_ICH_48MR143212CLK_CPU_BCLK2<19>CLK_CPU0#R1282 R14721<23>221<29>CLK_PCI0=0,PinCLK_PCI1=0,PinareCLK_SRC3R10612CLK_SRC3#R102122<23>125<26>R68412422<28>PE_REQ1#2R6851321<32>PE_REQ2#221<25>12CLK_PCIE_VGA291<33>CLK_SRC2#212CLK_PCIE_VGA#1R10012821<17>CLK_PCIE_SATA2CLK_SRC4#112<11,12,38>CLK_PCIE_SATA#1CLK_SRC6R67822<11,12,38>CLK_EZ_CLK2CLK_EZ_CLK2#1CLK_SRC6#R6792121475_0402_1%2CLK_SRC712CLK_EZ_CLK1CLK_SRC7#R10912CLK_EZ_CLK1#2CLK_SRC1R1212CLK_PCIE_ICH121CLK_SRC1#R1172CLK_PCIE_ICH#13<19>CLK_SRC0R1292CLK_DREF_SSCCLK_SRC0#R12522CLK_DREF_SSC#R136R1312CLK_DREF_96M21261213<19>VGATE1312CLK_14M_SIO12@@CompalElectronics,11CLKSEL0CLKSEL12222MCH_CLKSEL1SCHEMATIC,M/BLA-12211221CPU_BSEL0CPU_BSEL1@@DocumentRev¬P期四,十二月30,D 1DD2G2GSS211ClockKCFBM-L11-201209-11222222*12KCFBM-L11-201209-111222Table:ICS111172PM_STP_PCI#CLK_PCI2=1,PinarePEREQ#PM_STP_CPU#21212R124122CLK_MCH_BCLK12CLK_CPU1#1212CLK_MCH_BCLK#12R1342CLK_ICH_48MR143212CLK_CPU_BCLK2<19>CLK_CPU0#R1282 R14721<23>221<29>CLK_PCI0=0,PinCLK_PCI1=0,PinareCLK_SRC3R10612CLK_SRC3#R102122<23>125<26>R68412422<28>PE_REQ1#2R6851321<32>PE_REQ2#221<25>12CLK_PCIE_VGA291<33>CLK_SRC2#212CLK_PCIE_VGA#1R10012821<17>CLK_PCIE_SATA2CLK_SRC4#112<11,12,38>CLK_PCIE_SATA#1CLK_SRC6R67822<11,12,38>CLK_EZ_CLK2CLK_EZ_CLK2#1CLK_SRC6#R6792121475_0402_1%2CLK_SRC712CLK_EZ_CLK1CLK_SRC7#R10912CLK_EZ_CLK1#2CLK_SRC1R1212CLK_PCIE_ICH121CLK_SRC1#R1172CLK_PCIE_ICH#13<19>CLK_SRC0R1292CLK_DREF_SSCCLK_SRC0#R12522CLK_DREF_SSC#R136R1312CLK_DREF_96M21261213<19>VGATE1312CLK_14M_SIO12@@CompalElectronics,11CLKSEL0CLKSEL12222MCH_CLKSEL1SCHEMATIC,M/BLA-12211221CPU_BSEL0CPU_BSEL1@@DocumentRev¬P期四,十二月30,D 1DD2G2GSS211D2GS2222222222112222221111111101001011010CRT@@21RB411D_SOT23POLYSW112@2 1<22,27,33,38>2D_CRT_R5D_CRT_GD_CRT_BCRT-4PM@127126<16><8>129PM@FCM2012C-31126127<16><8><16><8>FCM2C-12PM@212812812GM@FCM2012C-3911111142222210Pfor5HS12FCM1608C-2112FCM1608C-11114<16>A221<8>2GM@SN74AHCT1G125GW_SOT353-33Pfor1214<16>AY1<8>GM@PM@12GM@12R11GM@21GMCH_CRT_DATA13<38>VGA_DDC_DATA13<38>VGA_DDC_CLK2R1GMCH_CRT_CLKGM@CompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D2121213513512132122113D2G21S3D2GS CRT_VSYNCPM@0_0402_5%21 CRT_HSYNCPM@0_0402_5%21CRT@@21RB411D_SOT23POLYSW112@2 1<22,27,33,38>2D_CRT_R5D_CRT_GD_CRT_BCRT-4PM@127126<16><8>129PM@FCM2012C-31126127<16><8><16><8>FCM2C-12PM@212812812GM@FCM2012C-3911111142222210Pfor5HS12FCM1608C-2112FCM1608C-11114<16>A221<8>2GM@SN74AHCT1G125GW_SOT353-33Pfor1214<16>AY1<8>GM@PM@12GM@12R11GM@21GMCH_CRT_DATA13<38>VGA_DDC_DATA13<38>VGA_DDC_CLK2R1GMCH_CRT_CLKGM@CompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D2121213513512132122113D2G21S3D2GS CRT_VSYNCPM@0_0402_5%21 CRT_HSYNCPM@0_0402_5%21LCDPOWER <8> <8><8> <8> <8>SN74AHCT1G125GW_SOT353-24AY1VGABOARDGM@2BypassCAPunderB+1352468GM@GM@D 7VGA_DDC_CLKVGA_DDC_DATA 9GM@22 11GS1VGA_TV_LUMA<15>VGA_TV_CRMA<15>2VGA_TV_COMPSVGA_CRT_HSYNCSUSP#VGA_CRT_VSYNCGM@GM@<15>GM@GM@22DVI_DETDVI_SCLKDVI_SDATA<22><22><22><22><22><22><22><22>1SDVO_SCLKSDVO_SDATCLK_PCIE_VGA@12<19><8,33>212<33>LCD/PANELBD.12135792DAC_BRIG344INVT_PWM6 578<8><8>89<8><8>GMCH_TXOUT0-GMCH_TXOUT0+<8><8><8><8>GMCH_TXOUT1-GMCH_TXOUT1+GMCH_TXOUT2+GMCH_TXOUT2-GMCH_TXCLK-GMCH_TXCLK+<8><8>DVI@ACES_88081-GM@ACES_87216-LCDPOWER <8> <8><8> <8> <8>SN74AHCT1G125GW_SOT353-24AY1VGABOARDGM@2BypassCAPunderB+1352468GM@GM@D 7VGA_DDC_CLKVGA_DDC_DATA 9GM@22 11GS1VGA_TV_LUMA<15>VGA_TV_CRMA<15>2VGA_TV_COMPSVGA_CRT_HSYNCSUSP#VGA_CRT_VSYNCGM@GM@<15>GM@GM@22DVI_DETDVI_SCLKDVI_SDATA<22><22><22><22><22><22><22><22>1SDVO_SCLKSDVO_SDATCLK_PCIE_VGA@12<19><8,33>212<33>LCD/PANELBD.12135792DAC_BRIG344INVT_PWM6 578<8><8>89<8><8>GMCH_TXOUT0-GMCH_TXOUT0+<8><8><8><8>GMCH_TXOUT1-GMCH_TXOUT1+GMCH_TXOUT2+GMCH_TXOUT2-GMCH_TXCLK-GMCH_TXCLK+<8><8>DVI@ACES_88081-GM@ACES_87216-CompalElectronics,DocumentRev¬P期四,十二月30,D31 12 3 1122 111 @0.1U_0402_25V4K @0.1U_0402_25V4K@0.1U_0402_25V4K@0.1U_0402_25V4K@11111<23,25,26,28>PCI_REQ#0PCI_GNT#0PCI_REQ#1PCI_GNT#1PCI_REQ#2PCI_GNT#2PCI_REQ#3PCI_GNT#3D_USB_SMI#1D_USB_SMI#2PCI_C/BE#0PCI_C/BE#1PCI_C/BE#2PCI_C/BE#3PCI_IRDY#PCI_PARPCI_RST#PCI_DEVSEL#PCI_PERR#PCI_SERR#PCI_STOP#PCI_TRDY#PLT_RST#CLK_PCI_ICH<23,25,26,28><23><23>PCI_PIRQE#PCI_PIRQF#PCI_PIRQG#PCI_PIRQH#@1@187223645CompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D 1211 2 3 <23,25,26,28>PCI_REQ#0PCI_GNT#0PCI_REQ#1PCI_GNT#1PCI_REQ#2PCI_GNT#2PCI_REQ#3PCI_GNT#3D_USB_SMI#1D_USB_SMI#2PCI_C/BE#0PCI_C/BE#1PCI_C/BE#2PCI_C/BE#3PCI_IRDY#PCI_PARPCI_RST#PCI_DEVSEL#PCI_PERR#PCI_SERR#PCI_STOP#PCI_TRDY#PLT_RST#CLK_PCI_ICH<23,25,26,28><23><23>PCI_PIRQE#PCI_PIRQF#PCI_PIRQG#PCI_PIRQH#@1@187223645CompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D 1211 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 PCIGNT[0]# Interrupt InternalPull-Samplehighdestinationis@1 2 3 4 213421LPC_AD0LPC_AD1LPC_AD2LPC_AD3211211@LPC_DRQ#121LPC_FRAME#closetoRAM 12EC_GA20H_A20M#<4>@R520122H_CPUSLP#H_DPRSTP#R180@2H_DPSLP#12H_FERR#H_PWH_PWRGOODMAINPWON@H_IGNNE# C@@212H_INIT#H_INTRB12E12<29,34><29,34>ICH21EC_KBRST#12 <29,34>H_NMIH_SMI#<29><34>H_STPCLK#21<29,34><33>IDE_DCS1#IDE_DCS3#IDE_DD[0..15]<21><21><14><14>1212<21><21>IDE_DIOW2<21><21>IDE_DIOW<21>IDE_DDREQPlacenearICH621@21@21SATA_ITX_C_DRX_N0@21SATA_ITX_C_DRX_P0@213421LPC_AD0LPC_AD1LPC_AD2LPC_AD3211211@LPC_DRQ#121LPC_FRAME#closetoRAM 12EC_GA20H_A20M#<4>@R520122H_CPUSLP#H_DPRSTP#R180@2H_DPSLP#12H_FERR#H_PWH_PWRGOODMAINPWON@H_IGNNE# C@@212H_INIT#H_INTRB12E12<29,34><29,34>ICH21EC_KBRST#12 <29,34>H_NMIH_SMI#<29><34>H_STPCLK#21<29,34><33>IDE_DCS1#IDE_DCS3#IDE_DD[0..15]<21><21><14><14>1212<21><21>IDE_DIOW2<21><21>IDE_DIOW<21>IDE_DDREQPlacenearICH621@21@21SATA_ITX_C_DRX_N0@21SATA_ITX_C_DRX_P0@21SATA_ITX_C_DRX_N221SATA_ITX_C_DRX_P2CompalElectronics,SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D AC-222131R20322EC_SW2<33>EC_SWEZ_PCIE_RXN1EZ_PCIE_RXP1EZ_PCIE_TXN1EZ_PCIE_TXP11@0.1U_0402_16V4Z2121@0.1U_0402_16V4Z122EZ_PCIE_RXN2EZ_PCIE_RXP2EZ_PCIE_TXN2EZ_PCIE_TXP22121@0.1U_0402_16V4Z<14><14>1@0.1U_0402_16V4Z2122EC_SW2<29><35>222<6>21<33,38><33><33,42,45>12<33><33><14><35><14,48><16><21>2CLK_PCIE_ICH#CLK_PCIE_ICH2<36><35><25,26,28,32,33><21><21>2212R67621USB_OC#42<23,32,33><33>USB_OC#6USB_OC#0112SYS_PW21<6,14,48>USB_OC#22USB20_N0USB20_P043215<33><33>67USB20_N2USB20_P28SYS_PWUSB20_N4USB20_P4USB20_N5USB20_P5USB20_N6USB20_P6<39>SYS_PW12EC_SW2<33>EC_SWEZ_PCIE_RXN1EZ_PCIE_RXP1EZ_PCIE_TXN1EZ_PCIE_TXP11@0.1U_0402_16V4Z2121@0.1U_0402_16V4Z122EZ_PCIE_RXN2EZ_PCIE_RXP2EZ_PCIE_TXN2EZ_PCIE_TXP22121@0.1U_0402_16V4Z<14><14>1@0.1U_0402_16V4Z2122EC_SW2<29><35>222<6>21<33,38><33><33,42,45>12<33><33><14><35><14,48><16><21>2CLK_PCIE_ICH#CLK_PCIE_ICH2<36><35><25,26,28,32,33><21><21>2212R67621USB_OC#42<23,32,33><33>USB_OC#6USB_OC#0112SYS_PW21<6,14,48>USB_OC#22USB20_N0USB20_P043215<33><33>67USB20_N2USB20_P28SYS_PWUSB20_N4USB20_P4USB20_N5USB20_P5USB20_N6USB20_P6<39>SYS_PW12<48><33><6,17,21,32,33><33>121214<14><14><33>O2@@11@CompalElectronics,@22SCHEMATIC,M/BLA-DocumentRev¬P期四,十二月30,D 212135GPOWERDIRECTMEDIAPCI-1 5 6 718 5 6 7 81NearPINF27(C155),121222+122111C121212121222NearPIN121122221211112NearPINNearA2-A6,D1-12NearPIN22221111212+5VALW112ICH6 122 221122E26,NearPIN111NearPIN212NearPIN221ICH61221211NearPIN21NearPIN12CompalElectronics,SCHEMATIC,M/BLA-DocumentRevD ¬P期四,十二月30, 1111NearPINF27(C155),121222+122111C121212121222NearPIN121122221211112NearPINNearA2-A6,D1-12NearPIN22221111212+5VALW112ICH6 122 221122E26,NearPIN111NearPIN212NearPIN221ICH61221211NearPIN21NearPIN12CompalElectronics,SCHEMATIC,M/BLA-DocumentRevD ¬P期四,十二月30, 1111USB1112221122HDDHOTCDROM<18> IDE_DA[0 <18> 1357911112468IDE_LED#9<18>#DY#Q21<33><18><18><18><18>1@FOXCONNQL11253-1@AOS31<19>B4Y11@2122A1@1@1121@12CDR_PSW1@212121@ 1@IDE_HRESET#1<19>4Y22<19><6,17,19,32,33>A1@CDROM135 135246<29><29>INT_CD_R24617987981@21@1@D2G1@SIDE_DIOW1111CDR_PSW1@222221@21@121OCTEK_CDR-@1@2D2G1@SCompalElectronics,1@1@HDDHOTCDROM<18> IDE_DA[0 <18> 1357911112468IDE_LED#9<18>#DY#Q21<33><18><18><18><18>1@