2024年-ispLever使用教程演示幻灯片

1、VHDL的文本方式设计ISPLEVER软件的使用方法1点击程序－>LatticeSemiconductor—>ispLEVERProjectNavigator2点击File—>NewProject3输入项目名，选VHDL，点下一步4选器件5点击下一步6点击完成78点击Source—New9选VHDLModule10填入文件名、实体名（两者要一致）和结构体名11点OK1213输入程序14保存15退出1617点击dff1(dff1.vhd)18双击SynplifySynthesizeVHDLFile源程序编写完成以后是综合192021双击VHDLTestBenchTemplate2223双击GenerateSchematicSymbol2425点击器件ispLSI1032E-70LJ8426双击FitDesign27282930下载3132333435362、VHDL的原理图方式设计（八）ISPLEVER软件的使用方法37点击File—>NewProject3839选器件40点击下一步41点击完成4243点击Source—New44454647484950后面的操作同前51作业：用VHDL语言：1、设计一个3线－8线译码器；2、设计一个上升沿触发JK触发器。CLRJQK52libraryieee;useieee.std_logic_1164.all;entitydff1isport(clk,d:instd_logic;q:outstd_logic);end;architecturertlofdff1isbeginprocess(clk)beginif(clk'eventandclk='1')thenq<=d;endif;endprocess;endrtl;53libraryieee;useieee.std_logic_1164.all;entityand_gateisPORT(A,B:INstd_logic;X:OUTstd_logic);end;architecturertlofand_gateisbeginX<=AANDB;endrtl;54libraryieee;useieee.std_logic_1164.all;entitydecoder_38isPORT(input:INstd_logic_vector(2downto0);output:OUTstd_logic_vector(7downto0));end;architecturertl1ofand_gateisbeginX<=AANDB;endrtl1;55libraryieee;useieee.std_logic_1164.all;entitydecoderisPORT(input:INstd_logic_vector(2downto0);output:OUTstd_logic_vector(7downto0));end;architecturertl1ofdecoderisbeginprocess(input)caseinputiswhen0=>output<="11111110";when1=>output<="11111101";when2=>output<="11111011";when3=>output<="11110111";when4=>output<="11101111";when5=>output<="11011111";when6=>output<="10111111";when7=>output<="01111111";endcase;endprocess;endrtl1;56libraryieee;useieee.std_logic_1164.all;entitydecoderisPORT(input:INstd_logic_vector(2downto0);yout:OUTstd_logic_vector(7downto0));end;architecturertl1ofdecoderisbeginprocess(input)caseinputiswhen"000"=>yout<="11111110";when"001"=>yout<="11111101";when"010"=>yout<="11111011";when"011"=>yout<="11110111";when"100"=>yout<="11101111";when"101"=>yout<="11011111";when"110"=>yout<="10111111";when"111"=>yout<="01111111";endcase;endprocess;endrtl1;57libraryieee;useieee.std_logic_1164.all;entityym3_8isport(a:instd_logic_vector(2downto0);y:outstd_logic_vector(7downto0));endym3_8;architecturertlofym3_8isbeginprocess(a)caseaiswhen"000"=>y<="11111110";when"001"=>y<="11111101";when"010"=>y<="11111011";when"011"=>y<="11110111";when"100"=>y<="111011