基于ISE14.7的Fpga基础教程

基于ISE14.7的Fpga基础教程BVTZeroLiucontentWhatistheFPGAFPGAdesign

flowProjectenvironment：ISE14.7VerilogexamplesFunctionalsimulationProgramanddebugWHATIStheFPGAPartoftheGraphitecircuitWhatcanFPGAdo?FPGA: FieldProgrammableGatearrayPLD: ProgrammableLogicDeviceCPLD: ComplexProgrammableLogicDeviceWHATIStheFPGAI/O:

pinsconnectedtoperipheralcircuitPLL:

frequencymultiplication,frequency

demultiplicationandphaseshiftMUTIPLIERM4KBLOCK: Memoryblock,forRAMROMandFIFOdesignLOGICARRAY ForcombinatorylogicandtriggerdesignProgramanddebugblock:

StructureofFPGAWHATIStheFPGASummaryofspartan-3AFPGAattributesNOTECLB:configurablelogicblockDCM:digitalclockmanagerDeviceutilizationofGraphiteFPGA(XC3S400A)FPGADESIGNFLOW——implementationISEFunctionaldescriptionReferencetohwspec.&FPGAspec.DesigninputSchematicorHDL(RTL)PinassignmentPlannerorTCLscriptSynthesisOutputgate-levelnetlistbasedonsomekindofFPGALogicaldescriptiontospecificdevicesPlace&routeDownloadandverifyFPGADESIGNFLOW——verificationThreekeyverificationpointsforFPGAimplementationBehavioralsimulationPost-place&routestatictiminganalysisDownloadandverifyincircuitPost-synthesisgate-levelsimulationandpost-place&routetimingsimulationscanbedoneforproductionsignoffPost-place&routetiming

simulationsarealsooftendone

toverifyboard-andsystem-leveltiming7IDE

(

integrated

development

environment

)THEMAININTERFACEOFISE14.7

DesignSpec.andprocessBVTFPGAdesignprocessReferenceDocuments:HWspec.SchematicFPGAspec.FPGAdesignprocessGraphitedocuments1,Createanewproject2,Projectname,locationandsourcetype3,ChosedeviceandtoolsIDE:createanewproject4,FinishIDE

Anewproject工程名器件名字生成了空的工程框架ide

Create/addnewsourceIDE

Acompletedprojectprojectfiles——(*.v)模块开始和结束（figure1）变量声明（figure2）数据流语句低层模块实例（figure3）行为描述块任务和函数Figure1Figure3Figure2Verilogstandard——purposePurpose:LessspaceHighersanitaryEasytoanalyzeanddebugEasytoreadandunderstandPortabilityVerilogstandard——Standardizeddesign

结构层次化命名规范化常量参数化其他Clock：避免混合时钟，避免门控时钟，单模块单时钟Reset：避免模块内部产生Always：敏感变量完备化……projectfiles——（*.ucf）SchematicviewStep1:viewschematicStep2:choosestartupSchematicviewChooseelementstocreateschematicSchematicviewGraphitesignal:<NOR_FLASH_RESET_L>FunctionalsimulationFunctionalsimulationFunctionalsimulationSimulationtool：isimGraphite：PID_LED_CONTROLsimulationReferencedocumentsFigure:LEDcontrol,fromGraphiteschematicFigure:ledbehaviordescription,fromGraphiteFPGAspec.Simulationtool：isimGraphite：resettimingsimulationProgramanddebug——compileFailedsuccessfulProgramanddegub——startimpactimpact——select/addstoragedeviceimpact——generatingpromfile*.mcsfile*.xsvffil