数字逻辑设计 - 存储器与可编程逻辑阵列

存储器与可编程逻辑阵列数字系统设计22015

ZDMCComputer

System

计算机系统数字系统设计32015

ZDMCROM（Read

Only

Memory），只读存储器

ROM是各种存储器中结构最简单的一种。在正常工作时它存储的数据是固定不变的，只能读出，不能随时写入.分类

固定ROM：无法更改，出厂时厂家编程

可编程ROM（PROM）：用户可写入一次

可擦可编程ROM（EPROM）：紫外线擦除

电抹可编程ROM（EEPROM）:电可擦4电路结构框图

n线---2n线译码器

二进制译码器数字系统设计地址输入容量概念：地址线：A0A1...An-10单元1单元W0W1

.

.

.2n-1单元...D0

D1Db-1

数据输出

“位”线：数据线“字”线：只有一个有效

2015

ZDMC地址译码器输出缓冲器三态

OE控制

.

.

.W2n−1

容量=字×位=

2n

×b（bits）例

EPROM

27256共有15位地址，8位输出，其容量：

215

×

8

=

262144

=

256K注意：1k=10241M=1024K1G=1024M核心

存储矩阵有

高电平，D1=0源负载字线处于低电平，

单

0=1。

矩阵4×2存储

D

元

D0

=W0

+W25

CMOS-ROM

2-4线译码器地址码输入端111W0

=

AA0W1

=

A1A0W2

=

AA0W3

=

AA0

2015

ZDMC输出缓冲器

数字系统设计没接MOS，字线处于表示存0=00时，W0=1，MOS导通，

接MOS表示存储“1”A

A储“0”

1地址译码器实现“与”功能：与阵列

存储矩阵实现“或”功能：“或阵”

D1

=W1+W2

+W3

数字系统设计62015

ZDMCTypical

timing

for

a

ROM

read

operation7

存储矩阵即为或阵列把乘积

项组合成m个逻辑函数输出。

地址译码器产生2n个字线即为固定与阵列产生2n个乘积项

输入地址信号即为电路的输入逻辑变量另外：ROM看成查找表（LUT，Look-Up

Table）系统

数字系统设计

2015

ZDMCROM应用

(ROM

Applications)十进制数（最小项）二进制码格雷码十进制数（最小项）二进制码格雷码B3B2B1B0R3R2R1R0B3B2B1B0R3R2R1R0000000000810001100100010001910011101200100011101010111130011001011101111104010001101211001010501010111131101101160110010114111010017011101001511111000数字系统设计82015

ZDMC

ROM为组合电路器件：

实现组合逻辑函数，实现时序电路

中组合逻辑部分.

方法：“查找表”，将真值表存于ROM中。例：用一个ROM实现二进制码到格雷码的转换

表

格雷码与二进制码关系对照表92015

ZDMC•确定地址和输出输入变量为B3、B2、B1、B0，地址为4位；函数R3、R2、R1、R0，输出为4个，应选用24×4的ROM•逻辑图：

ROM

24×40123A

015[0]A[1]A[2]A[3]A

CS

OE数字系统设计B0B1B2B3R0R1R2R3•存储内容（数据）：地址0数据D3D2D1D000000001001112……151000数字系统设计102015

ZDMC例.

用ROM和寄存器实现同时模10加/减可逆计数器，

X=0，加法；

X=1，减法。模10计数状态需4位，所以选用4位寄存器。根据时序电路结构，可得框图：Reg

CP图中组合电路由ROM实现；而由寄存器作记忆电路。Q44组合电路Y（进位）XDA数字系统设计112015

ZDMC•确定地址和输出输入变量为Q3、Q2、Q1、Q0和X，地址为5位；输出D3、D2、D1、D0和Y，5个，应选用25×5的ROM•逻辑图：•存储内容（数据）：

地址

数据00000000010000100010……0100001001010011000000000110010000010~151000010001……1100000111110010100026~310000001234ROM

25×5

0

[0]A

3

[1]A

1

[2]A

[3]A[4]ACSOEYQ0Q1Q2Q3CPREGX加法计数计数状态未用

减法状态未用A2A1A0B5B4B3B200000000010000010000101100101000100101011011010011111100数字系统设计122015

ZDMC例：用ROM设计一个组合电路，该电路输入是3位二进制数，输出是输入数值的平方。

列出组合电路的真值表。一般情况下真值表中所有可能的输入和输出都要列出。三个输入端对应8个字，每个字4位，因此ROM的容量是8x4。8x4ROMA0A1A2B0B10B2

B3B4

B5ROM真值表输入输出A2A1A0B5B4B3B2B1B0十进制00000000000010000011010000100401100100191000100001610101100125110100100361111100014913电路真值表

输出B0等于输入A0,输出B1一直为0.

本例中有三个输入端和四个输出端。数字系统设计

2015

ZDMC数字系统设计142015

ZDMCSARM

General

Memory

Operation(Static

Random-Access

Memory)Address

Decoder15Typical

SRAM

Organization:

16-word

x

4-bit++++

SRAM

Cell

SRAM

Cell

:

SRAM

Cell-

Sense

Amp

SRAM

Cell

SRAM

Cell

:

SRAM

Cell-

Sense

Amp

SRAM

Cell

SRAM

Cell

:

SRAM

Cell-

Sense

Amp

SRAM

Cell

SRAM

Cell

:

SRAM

Cell-

Sense

Amp

Word

0Word

1Word

15Dout

0

Dout

12015

ZDMCDout

2

Dout

3数字系统设计-+Wr

Driver-+Wr

Driver-+Wr

Driver-+Wr

DriverWrEnDin

0Din

1Din

2Din

3A0A1A2A3数字系统设计162015

ZDMC

Read

operation:

1.

Select

row

2.

Cell

pulls

one

line

low

and

one

high

3.

Sense

output

on

bit

and

bitWrite

operation:

1.

Drive

bit

lines

(e.g,

bit=1,

bit=0)

2.

Select

rowWhy

does

this

work?

When

one

bit-line

is

low,

it

will

force

output

high;

that

will

set

new

stateStatic

RAM

Cell

(静态随机访问存储器单元)Random-Access

Memory

6-Transistor

SRAM

Cellbitbitword(row

select)1001数字系统设计172015

ZDMC

Write

Enable

is

usually

active

low

(WE_L)Din

and

Dout

are

combined

to

save

pins:A

new

control

signal,

Output

Enable

(OE_L)

WE_L

is

asserted

(Low),

OE_L

is

unasserted

(High)

–

D

serves

as

the

data

input

pin

WE_L

is

unasserted

(High),

OE_L

is

asserted

(Low)

–

D

is

the

data

output

pin

Neither

WE_L

and

OE_L

are

asserted?

–

Chip

is

disconneted

Never

both

asserted!D2N

“words”

x

M

bit

SRAMM

A

NWE_LOE_LLogic

Diagram

of

a

Typical

SRAMor

chipSelect

(CS)

+

WERead

AccessTime18Typical

SRAM

TimingWrite

Timing:DRead

Timing:WE_L

数字系统设计A

Write

Hold

TimeWrite

Setup

Time

2015

ZDMCD2Nwords

x

M

bit

SRAMM

A

NWE_LOE_LData

InWrite

AddressOE_LHigh

ZRead

AddressJunkData

OutRead

Access

TimeData

OutRead

AddressOE

determines

direction

Hi

=

Write,

Lo

=

ReadWrites

are

dangerous!

Be

careful!

Double

signaling:

OE

Hi,

WE

Lo数字系统设计202015

ZDMC

ANDarray

ORarrayoutputs

•

•

•product

termsProgrammable

Logic

Arrays

(PLAs)

Pre-fabricated

building

block

of

many

AND/OR

gates

Actually

NOR

or

NAND

”Personalized"

by

making

or

breaking

connections

among

gates

Programmable

array

block

diagram

for

sum

of

products

form

•

•

•

inputs数字系统设计212015

ZDMCexample:F0F1F2F3====A

+A

C'B'

C'B'

CB'

C'+

AB

+

AB+

Ainput

side:

1

=

uncomplemented

in

term

0

=

complemented

in

term

–

=

does

not

participateproductpersonality

matrix

inputs

outputs

termABB'CAC'B'C'AA1–1–1B10–0–C–100–F000011F110100F210010F301001output

side:

1

=

term

connected

to

output

0

=

no

connection

to

output

reuse

of

termsEnabling

Concept

Shared

product

terms

among

outputs数字系统设计222015

ZDMC

Before

Programming

All

possible

connections

available

before

"programming"

In

reality,

all

AND

and

OR

gates

are

NANDs数字系统设计232015

ZDMCSimplified

PLD

Symbology数字系统设计242015

ZDMCABCF1F2F3F0

ABB'CAC'B'C'

A

After

Programming

Unwanted

connections

are

"blown"

Fuse

(normally

connected,

break

unwanted

ones)

Anti-fuse

(normally

disconnected,

make

wanted

connections)数字系统设计252015

ZDMCAB+A'B'

CD'+C'DAlternate

Representation

for

High

Fan-in

Structures

Short-hand

notation--don't

have

to

draw

all

the

wires

Signifies

a

connection

is

present

and

perpendicular

signal

is

an

input

to

gate

notation

for

implementing

F0

=

A

B

+

A'

B'

F1

=

C

D'

+

C'

D

A

B

C

D

AB

A'B'

CD'

C'D262015

ZDMC

A

B

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1

1数字系统设计C01010101F1

F20

00

10

10

10

10

10

11

1F3

F41

10

10

10

10

10

10

10

0F5

F60

01

11

10

01

10

00

01

1A'BCAB'C'AB'CABC'ABCA

B

CF1

F2

F3

F4

F5

F6full

decoder

as

for

memory

address

bits

stored

in

memory

A'B'C'

A'B'C

A'BC'Programmable

Logic

Array

Example

Multiple

functions

of

A,

B,

C

F1

=

A

B

CF2

=

A

+

B

+

CF3

=

A'

B'

C'F4

=

A'

+

B'

+

C'F5

=

A

xor

B

xor

CF6

=

(A

xnor

B

xnor

C)’001X01X011XX11XX001X01X000XX00XX00X101X101XX01XXW=A+BD+BCC

027DCA000000001111B000011110001C00110011001–D0101010101––W0000011111––X0000110000––Y0011111100––Z0110000110––DCD

A

BK-map

for

W

A

minimized

functions:

C

X

=

B

C'

Y=B+C

Z

=

A'B'C'D

+

B

C

D

+

A

D'

+

B'

C

D'数字系统设计

2015

ZDMC

BK-map

for

YPLA

Design

Example

BCD

to

Gray

code

converterD

A

B

K-map

for

X

A0

0

X

11

0

X

0

1

X

X1

0

X

X

B

K-map

for

Z数字系统设计282015

ZDMCW

XYZABDBCBC'BCA'B'C'DBCDAD'BCD'W=A+BD+BCX

=

B

C'Y=B+CZ

=

A'B'C'D

+

B

C

D

+

A

D'

+

B'

C

D'

not

a

particularly

good

candidate

for

PLA

implementation

since

no

terms

are

shared

among

outputs

however,

much

more

compact

and

regular

implementation

when

compared

with

discrete

AND

and

OR

gatesPLA

Design

Example

(cont’d)

Code

converter:

programmed

PLA

A

B

C

D

minimized

functions:01X001X011XX11XX00X110X001XX10XX00X101X101XX01XX01X001X000XX00XX29DCminimized

functions:

W=

X=

Y=

Z=数字系统设计A000000001111B000011110001C00110011001–D0101010101––W0000011111––X0000110000––Y0011111100––Z0110000110––DCD

A

BK-map

for

W

A

C2015

ZDMC

BK-map

for

YPLA

Design

Example

BCD

to

Gray

code

converterD

A

BK-map

for

X

A

BK-map

for

ZC01X0011X1X0X11XX00X1011X01XX01XX01X001X000XX00XXC

030D

minimized

functions:

W=

X=

Y=

Z=数字系统设计A000000001111B000011110001C00110011001–D0101010101––W0000011111––X0000110000––Y0011111100––Z0110000110––DCD

A

BK-map

for

W

A

C2015

ZDMC

BK-map

for

YPLA

Design

Example

#1

BCD

to

Gray

code

converterD

A

B

K-map

for

X

A0

0

X

11

0

X

0

1

X

X1

0

X

X

B

K-map

for

Z

CBC’数字系统设计322015

ZDMCmultiplexerdemultiplexer4x4

switchcontrolcontrolMultiplexer

/

Demultiplexer:

Making

Connections

Direct

point-to-point

connections

between

gatesMultiplexer:

route

one

of

many

inputs

to

a

single

outputDemultiplexer:

route

single

input

to

one

of

many

outputs数字系统设计332015

ZDMCfunctional

form

logical

form

two

alternative

forms

for

a

2:1

Mux

truth

tableA01ZI0I1I1000I0001A010Z00101111100111010100111Z

=

A'

I0

+

A

I1Multiplexers/Selectors

Multiplexers/Selectors:

general

concept

2n

data

inputs,

n

control

inputs

(called

"selects"),

1

output

Used

to

connect

2n

points

to

a

single

point

Control

signal

pattern

forms

binary

index

of

input

connected

to

output2n

-1In

general,

Z

=

Σ

(mkIk)ZmuxZ数字系统设计34

A

B

C

8:1muxZ

A

B2015

ZDMCA

2:1

mux:

Z

=

A'

I0

+

A

I1

4:1

mux:

Z

=

A'

B'

I0

+

A'

B

I1

+

A

B'

I2

+

A

B

I3

8:1

mux:

Z

=

A'B'C'I0

+

A'B'CI1

+

A'BC'I2

+

A'BCI3

+

AB'C'I4

+

AB'CI5

+

ABC'I6

+

ABCI7

k=0

in

minterm

shorthand

form

for

a

2n:1

Mux

I0

I1

I2

I3

I0

I4

I1

4:1

I5I0

2:1

I2

I6I1

mux

I3

I7Multiplexers/Selectors

(cont'd)I04:1I12:1mux4:12:135ZI0I1I2I3I4I5I6I7

alternative

implementation

2:1

8:1mux

mux

2:1mux

muxmux

2:1mux

C

A

B

Cascading

Multiplexers

Large

multiplexers

implemented

by

cascading

smaller

ones

8:1

mux

I2

mux

I3

Z

I4

I5

4:1

I6

mux

I7

B

C

Acontrol

signals

B

and

C

simultaneously

chooseone

of

I0,

I1,

I2,

I3

and

one

of

I4,

I5,

I6,

I7

control

signal

A

chooses

which

of

the

upper

or

lower

mux's

output

to

gate

to

Z

数字系统设计

2015

ZDMC数字系统设计362015

ZDMCCAB0121010001134

8:1

MUX567

S2

S1

S0F

Multiplexers

as

Lookup

Tables

(LUTs)

2n:1

multiplexer

implements

any

function

of

n

variables

With

the

variables

used

as

control

inputs

and

Data

inputs

tied

to

0

or

1

In

essence,

a

lookup

table

Example:

F(A,B,C)

=

m0

+

m2

+

m6

+

m7=

A'B'C'

+

A'BC'

+

ABC'

+

ABC=

A'B'(C')

+

A'B(C')

+

AB'(0)

+

AB(1)S1

S0372015

ZDMCA00001111B00110011C01010101F10100011C'C'01F01

4:1

MUX23

A

BC'C'01FCA数字系统设计B1010001101234

8:1

MUX567

S2

S1

S0Multiplexers

as

LUTs

(cont’d)

2n-1:1

mux

can

implement

any

function

of

n

variables

With

n-1

variables

used

as

control

inputs

and

Data

inputs

tied

to

the

last

variable

or

its

complementExample:

F(A,B,C)

=

m0

+

m2

+

m6

+

m7

=

A'B'C'

+

A'BC'

+

ABC'

+

ABC

=

A'B'(C')

+

A'B(C')

+

AB'(0)

+

AB(1)1011100011010110数字系统设计382015

ZDMC

Example:

F(A,B,C,D)

implemented

by

an

8:1

MUXn-1

mux

control

variables

single

mux

data

variablefour

possibleconfigurationsof

truth

table

rowscan

be

expressedas

a

function

of

Inchoose

A,B,C

as

control

variables

multiplexer

implementationGeneralization

I0I1.

.

.

In-1

InF........0100001In10In'111CAB0121D01D’DD’D’34

8:1

MUX567

S2

S1

S0DABCMultiplexers

as

LUTs

(cont’d)数字系统设计392015

ZDMC

1:2Decoder:

O0

=

G

•

S’

O1

=

G

•

S

2:4

Decoder:O0

=

G

•

S1’

•O1

=

G

•

S1’

•O2

=

G

•

S1

•O3

=

G

•

S1

•S0’S0

S0’

S0O0O1O2O3O4O5O6O7

3:8

Decoder:=

G

•

S2’

•

S1’

•

S0’=

G

•

S2’

•

S1’

•

S0=

G

•

S2’

•

S1

•

S0’=

G

•

S2’

•

S1

•

S0=

G

•

S2

•

S1’

•

S0’=

G

•

S2

•

S1’

•

S0=

G

•

S2

•

S1

•

S0’=

G

•

S2

•

S1

•

S0Demultiplexers

/

Decoders

Decoders

/

demultiplexers:

general

concept

Single

data

input,

n

control

inputs,

2n

outputs

Control

inputs

(called

“selects”

(S))

represent

binary

index

of

output

to

which

the

input

is

connected

Data

input

usually

called

“enable”

(G)数字系统设计402015

ZDMCdemultiplexer

generates

appropriate

Min-term

based

on

control

signals

(it

"decodes"

control

signals)Demultiplexers

as

General-Purpose

Logic

n:2n

decoder

implements

any

function

of

n

variables

With

the

variables

used

as

control

inputs

Enable

inputs

tied

to

1

and

Appropriate

min-terms

summed

to

form

the

functionA'B'C'A'B'CA'BC'A'BCAB'C'AB'CABC'ABC

0

1

2

33:8

DEC

4

5

6

7S2

S1

S0A

B

C“1”数字系统设计41

F1F2F3Demultiplexers

as

General-Purpose

Logic

(cont’d)

F1

=

A'

B

C'

D

+

A'

B'

C

D

+

A

B

C

D

A'B'C'D'A'B'C'DA'B'CD'A'B'CDA'BC'D'A'BC'DA'BCD'A'BCDAB'C'D'AB'C'DAB'CD'AB'CDABC'D'ABC'DABCD'ABCD

0

1

2

3

4

5

64:16

7DEC

8

9

10

11

12

13

14

15F2

=

A

B

C'

D’

+

A

B

CF3

=

(A'

+

B'

+

C'

+

D')

Enable

A

B

C

D2015

ZDMC2:4

DECF3:8

DEC3S2

S1

S03:8

DEC3S2

S1

S03:8

DEC33:8

DEC

3S2

S1

S0数字系统设计422015

ZDMC7ECD

0

1

2

4

5

6S2

S1

S0

0

1

2

4

5

6

7A'BC'DE'

AB'C'D'E'

AB'CDECascading

Decoders

5:32

decoder

1x2:4

decoder

4x3:8

decoders

0

1

2

S1

S0

3

A

B01245670124567A'B'C'D'E'ABCDEECD2

-1数字系统设计decoder

0

n-1

Address2015

ZDMCn1111word[i]

=

0011word[j]

=

1010bit

lines

(normally

pulled

to

1

throughresistor

–

selectively

connected

to

0by

word

line

controlled

switches)

43ij0internal

organizationword

lines

(only

oneis

active

–

decoder

isjust

right

for

this)

Read-only

MemoriesTwo

dimensional

array

of

1s

and

0s

Entry

(row)

is

called

a

"word"

Width

of

row

=

word-sizeIndex

is

called

an

"address"

Address

is

inputSelected

word

is

output数字系统设计442015